DS00537A-page 6

© 1992 Microchip Technology Inc.

Serial EEPROM Endurance

Second, the cycling mode graph in Figure 5 indicates

that significantly different results can be achieved in

endurance testing using a block cycle mode than using

a byte cycle mode. The block mode is commonly used

by manufacturers to “speed up” the endurance charac-

terization process. However, endurance results usually

will appear much better for the block mode than the byte

mode, due to the high voltage variables discussed

earlier. The reason is that the voltage ramp rate is

significantly SLOWER, the high voltages are slightly

lower, thus less stressful for block cycling since the

capacitive load of the entire array is on the high voltage

charge pump. The capacitive load is much lower with a

single row or byte, which thus has a significantly faster

ramp rate. Also, there is not a polysilicon to polysilicon

stress for adjacent cells since all cells are at the same

potential. Most often, these factors combine to yield

lower failure rates for block cycling than for byte cycling.

Again, the test conditions must match the system condi-

tions.

Finally, increasing temperature also increases stress on

the cell. Microchip’s endurance characterization data

indicates that increasing temperature adds an activa-

tion energy (Ea) of 0.12eV on the cell. From a 25

°C to

85

°C ambient the acceleration factor is approximately

2.1. Therefore, the higher the temperature, the higher

the stress. These results will vary significantly with each

EEPROM manufacturer.

RECOMMENDED EEPROM

ENDURANCE TESTING

Microchip believes that EEPROM components should

be endurance tested to reflect system conditions. There-

fore, units are cycled to an alternating ONE and ZERO

pattern (checkerboard), then to an alternating ZERO

and ONE pattern (inverse checkerboard).

Again, since endurance characterization data indicates

that a random single bit fail is the primary first order

failure mode, endurance is defect density (def/cm2 or

segment of bit size) dependent. Therefore an expected

failure rate range by density can be established.

DETERMINING THE RELIABILITY

CALCULATIONS

There are three primary components for the system

design engineers to use in determining the endurance

reliability required for a defect density limited applica-

tion. These three components are:

• Erase/write cycles/day estimated for the function.

• The number of bits in the function (or segment size).

• Case operating temperature of the Serial EEPROM.

Let’s look at three typical examples utilizing the above

information to predict a cumulative failure rate at differ-

ent points in a system lifetime. Please note that Industry

endurance perceptions have improved from a very high

(> 2%) failure rate expectation to a very low actual PPM

level failure rate in the past few years.

FIGURE 5 - CYCLING MODE EFFECT ON ENDURANCE TESTING

Erase/Write Cycles

Cumulative

Failure Rate

Byte Mode

Block Mode

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