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MIC4930 Datasheet(PDF) 15 Page - Microchip Technology

Part # MIC4930
Description  Hyper Speed Control짰 3A Buck Regulator
PDF  24 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MIC4930 Datasheet(HTML) 15 Page - Microchip Technology

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 2016 Microchip Technology Inc.
DS20005669A-page 15
MIC4930
RDSON. This improves efficiency by reducing DC
losses in the device. All but the inductor losses are
inherent to the device. In that case, inductor selection
becomes increasingly critical in efficiency calculations.
As the inductors are reduced in size, the DC resistance
(DCR) can become quite significant. The DCR losses
can be calculated as in Equation 5-3.
EQUATION 5-3:
From that, the loss in efficiency due to inductor DCR
and core losses (PCORE) can be calculated as in
Equation 5-4.
EQUATION 5-4:
5.5
External Ripple Injection
The MIC4930 control loop is ripple-based, and relies on
an internal ripple injection network to generate enough
ripple amplitude at the FB pin when negligible output
voltage ripple is present. The internal ripple injection
network is typically sufficient when recommended
R1-R2 and CF values are used. The FB ripple
amplitude should fall in the 20 mV to 100 mV range.
If significantly lower divider resistors and/or higher CF
values are used, the amount of internal ripple injection
may not be sufficient for stable operation. In this case,
external
ripple
injection
is
needed.
This
is
accomplished by connecting a series Rinj-Cinj circuit
between the SW and the FB pins, as shown in
FIGURE 5-1:
External Ripple Injection.
The injected ripple is:
EQUATION 5-5:
with Kdiv given by:
EQUATION 5-6:
In Equation 5-5 and Equation 5-6, it is assumed that
the time constant associated with CF must be greater
than the switching period.
EQUATION 5-7:
P
DCR
I
OUT
2
DCR
=
Efficiency Loss (%)
1
V
OUT
I
OUT
V
OUT
I
OUT
P
DCR
P
CORE
++
-------------------------------------------------------------------------------


–
100
=
MIC4930
PGND AGND
SW
GND
GND
VOUT
FB
Rinj
Cinj
R1
CF
R2
COUT
V
FB PP

V
IN
K
div
D
1
D
–

1
f
SW
--------------------
=
K
div
R1//R2
R
INJ
R1//R2
+
------------------------------------
=
1
f
SW
--------------------
T
---
1
«
=
Where:
VIN =
Power stage input voltage
D =
Duty cycle; VOUT/VIN
fSW =
Switching frequency
τ =
(R1//R2//Rinj) × CF



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