KSZ8091RNAIA datasheet(13/62 Pages) MICROCHIP

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 2016 Microchip Technology Inc.

DS00002298A-page 13

KSZ8091RNA/RND

3.2.1

RMII SIGNAL DEFINITION

Table 3-1 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.

3.2.1.1

Reference Clock (REF_CLK)

REF_CLK is a continuous 50MHz clock that provides the timing reference for TXEN, TXD[1:0], CRS_DV, RXD[1:0], and

RX_ER.

For RMII – 25 MHz Clock Mode, the KSZ8091RNA/RND generates and outputs the 50 MHz RMII REF_CLK to the MAC

at REF_CLK (Pin 16).

For RMII – 50 MHz Clock Mode, the KSZ8091RNA/RND takes in the 50 MHz RMII REF_CLK from the MAC or system

board at XI (Pin 8) and leaves the REF_CLK (Pin 16) as no connect.

3.2.1.2

Transmit Enable (TXEN)

TXEN indicates that the MAC is presenting dibits on TXD[1:0] for transmission. It is asserted synchronously with the first

dibit of the preamble and remains asserted while all dibits to be transmitted are presented on the RMII. It is negated

before the first REF_CLK following the final dibit of a frame.

TXEN transitions synchronously with respect to REF_CLK.

3.2.1.3

Transmit Data[1:0] (TXD[1:0])

When TXEN is asserted, TXD[1:0] are the data dibits presented by the MAC and accepted by the PHY for transmission.

When TXEN is de-asserted, the MAC drives TXD[1:0] to either 00 for the idle state (non-EEE mode) or 01 for the LPI

state (EEE mode).

TXD[1:0] transitions synchronously with respect to REF_CLK

3.2.1.4

Carrier Sense/Receive Data Valid (CRS_DV)

The PHY asserts CRS_DV when the receive medium is non-idle. It is asserted asynchronously when a carrier is

detected. This happens when squelch is passed in 10 Mbps mode, and when two non-contiguous 0s in 10 bits are

detected in 100 Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.

While carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered dibit of the

frame through the final recovered dibit. It is negated before the first REF_CLK that follows the final dibit. The data on

RXD[1:0] is considered valid after CRS_DV is asserted. However, because the assertion of CRS_DV is asynchronous

relative to REF_CLK, the data on RXD[1:0] is 00 until receive signals are properly decoded.

3.2.1.5

Receive Data[1:0] (RXD[1:0])

For each clock period in which CRS_DV is asserted, RXD[1:0] transfers a dibit of recovered data from the PHY.

When CRS_DV is de-asserted, the PHY drives RXD[1:0] to either 00 for the idle state (non-EEE mode) or 01 for the LPI

state (EEE mode).

RXD[1:0] transitions synchronously with respect to REF_CLK.

TABLE 3-1:

RMII SIGNAL DEFINITION

RMII Signal

Name

Direction with Respect to

PHY, KSZ8091RNA/RND

Signal

Direction with

Respect to MAC

Description

REF_CLK

Output (25 MHz clock

mode)/

<no connect> (50 MHz

clock mode)

Input/

Input or

Synchronous 50 MHz reference clock for receive,

transmit, and control interface

TXEN

Input

Output

Transmit Enable

TXD[1:0]

Input

Output

Transmit Data[1:0]

CRS_DV

Output

Input

Carrier Sense/Receive Data Valid

RXD[1:0]

Output

Input

Receive Data[1:0]

RXER

Output

Input, or (not

required)

Receive Error

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