Agere Systems Inc.

21

Data Sheet, Rev. 1

October 2002

Two-Cable Transceiver/Arbiter Device

FW802C Low-Power PHY

IEEE 1394A-2000

The meaning of the register fields with the port status page are defined by Table 11 below.

Table 11. PHY Register Port Status Page Fields

Field

Size Type

Power Reset

Value

Description

AStat

2

r

—

TPA line state for the port:

BStat

2

r

—

TPB line state for the port (same encoding as AStat).

Child

1

r

0

If equal to one, the port is a child; otherwise, a parent. The

meaning of this bit is undefined from the time a bus reset is

detected until the PHY transitions to state T1: Child Hand-

shake during the tree identify process (see Section 4.4.2.2 in

Connected

1

r

0

If equal to one, the port is connected.

Bias

1

r

0

If equal to one, incoming TPBIAS is detected.

Disabled

1

rw

0

If equal to one, the port is disabled.

Negotiated_speed

3

r

000

Indicates the maximum speed negotiated between this PHY

port and its immediately connected port; the encoding is the

same as for the PHY register Max_speed field.

Int_enable

1

rw

0

Enable port event interrupts. When set to one, the PHY will

set Port_event to one if any of connected, bias, disabled, or

fault (for this port) change state.

Fault

1

rw

0

Set to one if an error is detected during a suspend or resume

operation. A write of one to this bit clears it to zero.