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LDAC Functionality

DAC5573 Registers

DAC5573 as a Slave Receiver—Standard and Fast Mode

SLAVE ADDRESS R/W

A Ctrl-Byte

A MS-Byte A

LS-Byte

A/A

P

0 (write)

Data Transferred

(n* Words + Acknowledge)

Word = 16 Bit

From Master to DAC5573

From DAC5573 to Master

A = Acknowledge (SDA LOW)

A = Not Acknowledge (SDA HIGH)

S = START Condition

Sr = Repeated START Condition

P = STOP Condition

1

0

0

1

1

A1

A0

R/W

MSB

LSB

Factory Preset

S

0 = Write to DAC5573

1 = Read from DAC5573

DAC5573

SLAS401 – NOVEMBER 2003

Depending on the control byte, DACs are synchronously updated on the falling edge of the acknowledge signal

that follows LS byte. The LDAC pin is required only when an external timing signal is used to update all the

channels of the DAC asynchronously. LDAC is a positive edge triggered asynchronous input that allows four

DAC output voltages to be updated simultaneously with temporary register data. The LDAC trigger should only

be used after the buffer's temporary registers are properly updated through software.

Table 3. DAC5573 Architecture Register Descriptions

REGISTER

DESCRIPTION

CTRL[7:0]

Stores 8-bit wide control byte sent by the master

MSB[7:0]

Stores the 8 most significant bits of unsigned binary data sent by the master. Can also store 2-bit power-down data.

TRA[9:0], TRB[9:0],

10-bit temporary storage registers assigned to each channel. Two MSBs store power-down information, 8 LSBs

TRC[9:0], TRD[9:0]

store data.

DRA[9:0], DRB[9:0],

10-bit DAC registers for each channel. Two MSBs store power-down information, 8 LSBs store DAC data. An

DRC[9:0], DRD[9:0]

update of this register means a DAC update with data or power down.

Figure 33 shows the standard and fast mode master transmitter addressing a DAC5573 Slave Receiver with a

7-bit address.

Figure 33. Standard and Fast Mode: Slave Receiver

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