DS4510U-5SLASHT datasheet(7/12 Pages) MAXIM

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CPU Supervisor with Nonvolatile Memory and

Programmable I/O

_____________________________________________________________________

transistors. Read the I/O status register (F8h) to deter-

mine the logic levels present at the I/O pins.

User Memory

Three types of memory are present in the DS4510

(EEPROM, SEEPROM, and SRAM). The main user

memory is 64 bytes of EEPROM starting at address

00h. This memory is not SRAM shadowed, so all writes

to these locations result in EEPROM write cycles

regardless of the state of the

SEE bit. Additional memo-

ry for storing application data includes 6 bytes of SRAM

(FAh–FFh), and 2 bytes of SEEPROM (F2h, F3h). Refer

to the register memory map (Figure 3) for register

addresses and memory types. Figure 4 shows the bit

names for the memory-mapped I/O bytes and their fac-

tory default values.

The higher-order bits of the I/O registers that are not

used, such as the four most significant bits of the

pullup-enable byte (address F0h), can be used as

additional memory. It is the responsibility of the appli-

cation to ensure that writes to these bytes do not

adversely affect bits controlling special functions of the

DS4510.

I/O STATUS

SRAM

MEMORY TYPE

Figure 2. How to Read the Memory Map

tRPU

tRPD

VOH

VOL

VCCTP (MAX)

VCCTP (MIN)

VCCTP

Figure 1. CPU Supervisor Power-Up and Power-Down Timing

PULLUP ENABLE

SEE

RESET DELAY

SEE

USER BYTE

SEE

USER BYTE

SEE

I/O3 CONTROL

SEE

I/O2 CONTROL

SEE

I/O1 CONTROL

SEE

I/O0 CONTROL

SEE

I/O STATUS

SRAM

CONFIG

USER BYTE

SRAM

USER BYTE

RESERVED

USER BYTE

User byte

USER BYTE

*ITALICIZED BYTES HAVE BIT DESCRPTIONS, REFER TO FIGURE 3.

Figure 3. Register Memory Map

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