RTC4543 datasheet(2/2 Pages) ETC

2 / 2 page

Real time clock module

FDT

MSB

Seconds (0 to 59)

s 40

s 20

s 10

s 8

s 4

s 2

s 1

∗

Minutes (0 to 59)

mi 40

mi 20

mi 10

mi 8

mi 4

mi 2

mi 1

∗

Hour (0 to 23)

∗

h 20

h 10

h 8

h 4

h 2

h 1

Day of the week (1 to 7)

∗

w 4

w 2

w 1

∗

Day (1 to 31)

∗

d 20

d 10

d 8

d 4

d 2

d 1

Month (1 to 12)

∗

mo 10

mo 8

mo 4

mo 2

mo 1

y 80

year (0 to 99)

y 40

y 20

y 10

y 8

y 4

y 2

y 1

FDT bit: Supply voltage detection bit.

TM bit: Test bit always set this bit to "0".

Switching characteristics

Block diagram

Timing chart

32.768 kHz

FOUT

CLK

FSEL

FOE

DATA

(Ta=-40 to +85˚C, CL=30 pF)

Output

controller

I/O

controller

Control

circuit

Voltage

detecter

Divider

Oscillator

Clock and calendar

Shift register

FOE

FOUT

DATA

CLK

DATA

CLK

VIL

VIH

Enabled

High impedance

Disabled

tXZ

tf 2

tSD tHD

tDATA

tCLKH

tCES

tCLK

tWRS

tr1

tCE

tf1

tr1

tf1

tCEH

tOZ

tCEH

tRCV

tWRH

tCLKL

tr2

tZX

Duty=

x 100

[%]

Data read

Data write

FOUT

Disabled and Enabled

Item

CLK clock cycle

CLK high pulse width

CLK low pulse width

CE setup time

CE hold time

CE enable time

Write data setup time

Write data hold time

WR setup time

WR hold time

DATA output delay time

DATA output floating time

Clock input rise time

Clock input fall time

FOUT rise time

FOUT fall time

Disable time

Enable time

FOUT duty ratio

Wait time

Symbol

t CLK

t CLKH

t CLKL

t CES

t CEH

t CE

t SD

t HD

t WRS

t WRH

t DATA

t DZ

t r1

t f1

t r2

t f2

t XZ

t ZX

Duty

t rcv

Min.

0.75

0.375

—

0.1

100

—

0.95

Max.

7800

3900

—

0.9

—

0.2

0.1

100

—

Min.

1.5

0.75

—

0.2

0.1

100

—

1.9

Max.

7800

3900

—

0.9

—

0.4

0.2

100

200

—

Unit

µs

CL= 30pF

VDD= 5V± 10%

VDD= 3V± 10%

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