37B77X datasheet(85/196 Pages) SMSC

85 / 196 page

EPP DATA PORT 2

ADDRESS OFFSET = 06H

The EPP Data Port 2 is located at an offset of

'06H' from the base address.

Refer to EPP

DATA PORT 0 for a description of operation.

This register is only available in EPP mode.

EPP DATA PORT 3

ADDRESS OFFSET = 07H

The EPP Data Port 3 is located at an offset of

'07H' from the base address.

Refer to EPP

DATA PORT 0 for a description of operation.

This register is only available in EPP mode.

EPP 1.9 OPERATION

When

the

EPP

mode

selected

the

configuration register, the standard and bi-

directional modes are also available. If no EPP

Read, Write or Address cycle is currently

executing, then the PDx bus is in the standard or

bi-directional mode, and all output signals

(STROBE, AUTOFD, INIT) are as set by the

SPP Control Port and direction is controlled by

PCD of the Control port.

In EPP mode, the system timing is closely

coupled to the EPP timing. For this reason, a

watchdog timer is required to prevent system

lockup. The timer indicates if more than 10usec

have elapsed from the start of the EPP cycle

(nIOR or nIOW asserted) to nWAIT being

deasserted (after command).

If a time-out

occurs, the current EPP cycle is aborted and the

time-out condition is indicated in Status bit 0.

During an EPP cycle, if STROBE is active, it

overrides the EPP write signal forcing the PDx

bus to always be in a write mode and the

nWRITE signal to always be asserted.

37B77X Datasheet(PDF) 85 Page - SMSC Corporation

37B77X Datasheet(HTML) 85 Page - SMSC Corporation

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