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MAX5106EEE Datasheet(PDF) 16 Page - Maxim Integrated Products |
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MAX5106EEE Datasheet(HTML) 16 Page - Maxim Integrated Products |
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16 / 19 page ![]() Nonvolatile, Quad, 8-Bit DACs 16 ______________________________________________________________________________________ This initialization period takes about 80µs with the DAC registers loading first and the mute/shutdown register loading last. During this time, the DAC outputs are held in the mute state and the serial interface is disabled. Once the mute/shutdown register is loaded, the DAC outputs are updated to their stored data and operating states, and the serial interface is enabled. Applications Information DAC Linearity and Offset Voltage The output buffer can have a negative input offset volt- age that would normally drive the output negative, but since there is no negative supply, the output remains at GND (Figure 9). When linearity is determined using the end-point method, it is measured between code 10 (0Ahex) and full-scale code (FFhex) after the offset and gain error are calibrated out. With a single supply, neg- ative offset causes the output not to change with an input code transition near zero (Figure 9). Thus, the lowest code that produces a positive output is the lower endpoint. External Voltage Reference The MAX5105/MAX5106 have two reference inputs for each DAC, REFH_, and REFL_. REFH_ sets the full- scale voltage, while REFL_ sets the zero code output. REFL2 and REFL3 are internally connected to GND in the MAX5106. A 256k Ω typical input impedance at REFH_ is code independent. The output voltage from these devices can be represented by a digitally pro- grammable voltage source as follows: VOUT = [(VREFH_ - VREFL_) x (N / 256)] + VREFL_ where N is the decimal value of the DAC’s binary input code. Power Sequencing The voltage applied to REFH_ and REFL_ should not exceed VDD at any time. If proper power sequencing is not possible, connect an external Schottky diode between REFH_ and REFL_ and VDD to ensure compli- ance with the absolute maximum ratings. Do not apply signals to the digital inputs before the device is fully powered up. Power-Supply Bypassing and Ground Management Digital or AC transient signals on GND can create noise at the analog output. Return GND to the highest-quality ground available. Bypass VDD with a 0.1µF capacitor, located as close to the device as possible. Bypass REF_ to GND with a 0.1µF capacitor. Carefully printed circuit board ground layout minimizes crosstalk between the DAC outputs and digital inputs. Chip Information TRANSISTOR COUNT: 32,000 PROCESS: CMOS |
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