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PI74AVC16821 Datasheet(PDF) 1 Page - Pericom Semiconductor Corporation |
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PI74AVC16821 Datasheet(HTML) 1 Page - Pericom Semiconductor Corporation |
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1 / 10 page ![]() 1 PS8548 07/31/01 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI74AVC+16821 2.5V 20-Bit Bus Interface Flip-Flop with 3-State Outputs Logic Block Diagram Product Features PI74AVC +16821 is designed for low-voltage operation, VCC = 1.65V to 3.6V True ±24mA Balanced Drive @ 3.3V IOFF supports partial power-down operation 3.6V I/O Tolerant Inputs and Outputs All outputs contain a patented DDC (Dynamic Drive Control) circuit that reduces noise without degrading propagation delay Industrial operation: 40°C to +85°C Available Packages: 56-pin 240 mil wide plastic TSSOP (A) 56-pin 173 mil wide plastic TVSOP (K) Description Pericom Semiconductors PI74AVC+ series of logic circuits are produced using the Companys advanced submicron CMOS technology, achieving industry leading speed. ThePI74AVC+16821isa20-bit businterfaceflip-flopdesignedfor 1.65V to3.6V VCCoperation. Itcanbeusedastwo10-bitflip-flops or one 20-bit flip-flop. The 20 flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs. A buffered output-enable (OE) input can be used to place the ten outputsineitheranormallogicstate(HIGHorLOWlevel)orahigh- impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capacity to drive bus lines without the need for interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. 1 OE C1 1 D 1CLK TO 9 OTHER CHANNELS 1D1 1 Q1 1 56 55 2 One of Ten Channels 2 OE C1 1 D 2CLK TO 9 OTHER CHANNELS 2D1 2Q1 28 29 42 15 One of Ten Channels |
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