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PSMN005 Datasheet(PDF) 2 Page - NXP Semiconductors |
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PSMN005 Datasheet(HTML) 2 Page - NXP Semiconductors |
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2 / 12 page ![]() October 1999 2 Rev 1.200 Philips Semiconductors Product specification PSMN005-55B; PSMN005-55P N-channel logic level TrenchMOS(TM) transistor FEATURES SYMBOL QUICK REFERENCE DATA • ’Trench’ technology V DSS = 55 V • Very low on-state resistance • Fast switching I D = 75 A • Low thermal resistance R DS(ON) ≤ 5.8 mΩ (VGS = 10 V) R DS(ON) ≤ 6.3 mΩ (VGS = 5 V) GENERAL DESCRIPTION SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in each package at each voltage rating. Applications:- • d.c. to d.c. converters • switched mode power supplies The PSMN005-55P is supplied in the SOT78 (TO220AB) conventional leaded package. The PSMN005-55B is supplied in the SOT404 surface mounting package. PINNING SOT78 (TO220AB) SOT404 (D 2PAK) PIN DESCRIPTION 1 gate 2 drain 1 3 source tab drain LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V DSS Drain-source voltage T j = 25 ˚C to 175˚C - 55 V V DGR Drain-gate voltage T j = 25 ˚C to 175˚C; RGS = 20 kΩ -55 V V GS Continuous gate-source - ± 15 V voltage V GSM Peak pulsed gate-source T j ≤ 150 ˚C - ± 20 V voltage I D Continuous drain current T mb = 25 ˚C; VGS = 5 V - 75 2 A T mb = 100 ˚C; VGS = 5 V - 75 2 A I DM Pulsed drain current T mb = 25 ˚C - 240 A P D Total power dissipation T mb = 25 ˚C - 230 W T j, Tstg Operating junction and - 55 175 ˚C storage temperature d g s 13 tab 2 12 3 tab 1 It is not possible to make connection to pin:2 of the SOT404 package 2 maximum current limited by package |
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