ADUCM331WDCPZ datasheet(7/16 Pages) AD

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Data Sheet

ADuCM330/ADuCM331

Rev. C | Page 7 of 16

TA = −40°C to +115°C

TA = +115°C to

+125°C1

Parameter

Test Conditions/Comments

Min

Typ

Max

Typ

Unit

PROCESSOR START-UP TIME1

At Power-On

Includes kernel power-on execution

time, VDD drops to < 0.8 V

Brownout

VDD drops below power on reset

voltage but not below 0.8 V

1.15

After Reset Event

Includes kernel power-on execution

time

1.25

Wake-Up from LIN

0.15

LIN INPUT/OUTPUT GENERAL1

Baud Rate

1000

20,000

Bits/sec

VDD

Supply voltage range for which the

LIN interface is functional

LIN Comparator Response

Time

µs

LIN DC PARAMETERS

ILIN_DOM_MAX

Current limit for driver when LIN bus is

in dominant state, VBAT = VBAT

(maximum)

200

ILIN_PAS_REC1

Driver off, 7.0 V < VBUS < 18 V, VDD =

VLIN − 0.7 V

µA

ILIN_PAS_DOM1

Input leakage, VLIN = 0 V, VBAT = 12 V,

driver off

−1

ILIN_NO_GND1, 22

Control unit disconnected from

ground, GND = VDD, 0 V < VLIN <

18 V, VBAT = 12 V

−1

IBUS_NO_BAT1

VBAT disconnected, VDD = GND, 0 V <

VBUS < 18 V

µA

VLIN_DOM1

LIN receiver dominant state, VDD > 7.0 V

0.4 × VDD

VLIN_REC1

LIN receiver recessive state, VDD > 7.0 V

0.6 VDD

VLIN_CNT1

VLIN_CNT = (VTH_DOM + VTH_REC)/2, VDD > 7.0 V

0.475 ×

VDD

0.5 ×

VDD

0.525 ×

VDD

VHYS1

VHYS = VTH_REC − VTH_DOM

0.175 ×

VDD

VLIN_DOM_DRV_LOSUP1

LIN dominant output voltage, VDD =

7.0 V

RL = 500 Ω

1.2

RL = 1000 Ω

0.6

VLIN_DOM_DRV_HISUP1

LIN dominant output voltage, VDD =

18 V

RL = 500 Ω

RL = 1000 Ω

0.8

VLIN_RECESSIVE1

LIN recessive output voltage

0.8 × VDD

VBAT Shift1,22

0.115 ×

VDD

GND Shift1,22

0.115 ×

VDD

RSLAVE

Slave termination resistance

kΩ

VSERIAL_DIODE1

Voltage drop at the serial diode,

DSer_Int

0.4

0.7

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