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18F452 Datasheet(PDF) 31 Page - Microchip Technology |
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18F452 Datasheet(HTML) 31 Page - Microchip Technology |
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31 / 332 page  2002 Microchip Technology Inc. DS39564B-page 29 PIC18FXX2 FSR1H 242 442 252 452 ---- xxxx ---- uuuu ---- uuuu FSR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu BSR 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu INDF2 242 442 252 452 N/A N/A N/A POSTINC2 242 442 252 452 N/A N/A N/A POSTDEC2 242 442 252 452 N/A N/A N/A PREINC2 242 442 252 452 N/A N/A N/A PLUSW2 242 442 252 452 N/A N/A N/A FSR2H 242 442 252 452 ---- xxxx ---- uuuu ---- uuuu FSR2L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu STATUS 242 442 252 452 ---x xxxx ---u uuuu ---u uuuu TMR0H 242 442 252 452 0000 0000 uuuu uuuu uuuu uuuu TMR0L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu T0CON 242 442 252 452 1111 1111 1111 1111 uuuu uuuu OSCCON 242 442 252 452 ---- ---0 ---- ---0 ---- ---u LVDCON 242 442 252 452 --00 0101 --00 0101 --uu uuuu WDTCON 242 442 252 452 ---- ---0 ---- ---0 ---- ---u RCON(4) 242 442 252 452 0--q 11qq 0--q qquu u--u qquu TMR1H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 242 442 252 452 0-00 0000 u-uu uuuu u-uu uuuu TMR2 242 442 252 452 0000 0000 0000 0000 uuuu uuuu PR2 242 442 252 452 1111 1111 1111 1111 1111 1111 T2CON 242 442 252 452 -000 0000 -000 0000 -uuu uuuu SSPBUF 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu SSPADD 242 442 252 452 0000 0000 0000 0000 uuuu uuuu SSPSTAT 242 442 252 452 0000 0000 0000 0000 uuuu uuuu SSPCON1 242 442 252 452 0000 0000 0000 0000 uuuu uuuu SSPCON2 242 442 252 452 0000 0000 0000 0000 uuuu uuuu TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes, they are disabled and read ’0’. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’. |
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