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MB91F467DA Datasheet(PDF) 128 Page - Cypress Semiconductor |
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MB91F467DA Datasheet(HTML) 128 Page - Cypress Semiconductor |
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128 / 137 page  Document Number: 002-04613 Rev. *A Page 128 of 137 MB91460D Series Bus hold timing (VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = 40°C to 105°C) Note : BRQ must be kept High until the bus is granted (this is acknowledged by the falling edge of BGRNTX). It must be kept High as long as the bus shall be hold. After releasing the bus (BRQ set to Low) this is acknowledged by the rising edge of BGRNTX. Parameter Symbol Pin name Value Unit Min Max MCLKO ↓ to BGRNTX delay time TCLBGL MCLKO BGRNTX —2 × tCLKT 16 ns TCLBGH — 2 × tCLKT 3ns Bus HIZ to BGRNTX ↓ TAXBGL BGRNTX MCLK* A0 to An RDX, ASX WRXn,WEX CSXn,BAAX tCLKT 1— ns BGRNTX ↑ to Bus drive TBGHAV tCLKT 1— ns MCLKO BRQ BGRNTX ADDR,RDX,WRX, WEX,CSXn,ASX, MCLKE,MCLKI, BAAX TCLBGL TAXBGL TBGHAV TCLBGH |
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