AD9142ABCPZRL datasheet(67/73 Pages) AD

67 / 73 page

AD9142A

Data Sheet

QDAC GAIN ADJUST REGISTER

Address: 0x40, Reset: 0x20, Name: QDAC_GAIN_ADJ

Table 84. Bit Descriptions for QDAC_GAIN_ADJ

Bits

Bit Name

Settings

Description

Reset

Access

[5:0]

QDAC_GAIN_ADJ

This register is the 6-bit digital gain adjust on the Q channel. The bit weighting

is MSB = 20, LSB = 2−5, which yields a multiplier range of 0 to 2 or −∞ to 6 dB.The

default gain setting is 0x20, which maps to unity gain (0 dB).

0x20

GAIN STEP CONTROL 0 REGISTER

Address: 0x41, Reset: 0x01, Name: GAIN_STEP_CTRL0

Table 85. Bit Descriptions for GAIN_STEP_CTRL0

Bits

Bit Name

Settings

Description

Reset

Access

[5:0]

RAMP_UP_STEP

This register sets the step size of the increasing gain.The digital gain increases by the

configured amount in every four DAC cycles until the gain reaches the setting in

IDAC_GAIN_ADJ (Register 0x3F).The bit weighting is MSB = 21, LSB = 2−4. Note that

the value in this register must not be greater than the values in the IDAC_GAIN_ADJ.

0x01

GAIN STEP CONTROL 1 REGISTER

Address: 0x42, Reset: 0x41, Name: GAIN_STEP_CTRL1

Table 86. Bit Descriptions for GAIN_STEP_CTRL1

Bits

Bit Name

Settings

Description

Reset

Access

DAC_OUTPUT_OFF

This bit allows for turning the DAC output on and off manually. The digital

IQ gain function (Register 0x27, Bit 5) must be turned on for this bit to function.

0x0

DAC_OUTPUT_STATUS

This bit indicates the DAC output on/off status. When the DAC output is turned

off, this bit is 1. Upon power-up, this bit is 1. The digital IQ gain function

(Register 0x27, Bit 5) must be turned on for this bit to track the on/off status

0x1

[5:0]

RAMP_DOWN_STEP

This register sets the step size of the decreasing gain. The digital gain

decreases by the configured amount in every four DAC cycles until the gain

reaches zero. The bit weighting is MSB = 21, LSB = 2−4. Note that the value in

this register must not be greater than the values in the IDAC_GAIN_ADJ

(Register 0x3F).

0x01

TX ENABLE CONTROL REGISTER

Address: 0x43, Reset: 0x07, Name: TX_ENABLE_CTRL

Table 87. Bit Descriptions for TX_ENABLE_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

TXENABLE_GAINSTEP_EN

DAC output gradually turns on/off under the control of the

TXENABLE signal from the TXEN pin according to the settings

in Register 0x41 and Register 0x42.

TXENABLE_SLEEP_EN

When set to 1, the device is put in sleep mode when the

TXENABLE signal from the TXEN pin is low.

TXENABLE_POWER_DOWN_EN

When set to 1, the device is put in power down mode when

the TXENABLE signal from the TXEN pin is low.

Rev. A | Page 66 of 72

AD9142ABCPZRL Datasheet(PDF) 67 Page - Analog Devices

AD9142ABCPZRL Datasheet(HTML) 67 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

Datasheet Download

Link URL