ZSC31010CEC datasheet(35/43 Pages) IDT

35 / 43 page

ZSC31010 Datasheet

January 20, 2016

Application Circuit Examples

Note: The typical output analog load resistor RL = 10 kΩ (minimum 2.5 kΩ). This optional load resistor can be

configured as a pull-up or pull-down. If it is configured as a pull-down, it cannot be part of the module to be

calibrated because this would prevent proper operation of the ZACwire™. If a pull-down load is desired, it must be

added to the system after module calibration.

There is no output load capacitance needed.

EEPROM contents: OUTPUT_select, JFET_Cfg, 1V_Trim/JFET-Trim

4.1.

Three-Wire Rail-to-Rail Ratiometric Output

This example shows an application circuit for rail-to-rail ratiometric voltage output configuration with temperature

compensation via internal PTAT. The same circuitry is applicable for a 0 to 1 V absolute analog output.

Figure 4.1

Rail-to-Rail Ratiometric Voltage Output

ZSC31010

Bsink

VBP

N/C

VBN

VSS

SIG

VDD

Vgate

0.1

Vsupply

Ground

+2.7 to +5.5 V

OUT

Optional Bsink

10 nF

The optional bridge sink allows power savings switching off the bridge current. The output voltage can be one of

the following options:

• Rail-to-rail ratiometric analog output V

DD (= Vsupply).

• 0 to 1 V absolute analog output. The absolute voltage output reference is trimmable 1 V (±3 mV) in the 1 V

output mode via a 4-bit EEPROM field (see section 2.4.3).

ZSC31010CEC Datasheet(PDF) 35 Page - Integrated Device Technology