X9410 datasheet(4/21 Pages) XICOR

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X9410

Characteristics subject to change without notice.

4 of 21

REV 1.1 10/6/00

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Write in Process

The contents of the Data Registers are saved to

nonvolatile memory when the CS pin goes from LOW

to HIGH after a complete write sequence is received by

the device. The progress of this internal write operation

can be monitored by a Write In Process bit (WIP). The

WIP bit is read with a Read Status command.

INSTRUCTIONS

Identification (ID) Byte

The ﬁrst byte sent to the X9410 from the host, following

a CS going HIGH to LOW, is called the Identiﬁcation

byte. The most signiﬁcant four bits of the slave address

are a device type identiﬁer, for the X9410 this is ﬁxed

as 0101[B] (refer to Figure 2).

The two least signiﬁcant bits in the ID byte select one of

four devices on the bus. The physical device address is

deﬁned by the state of the A0-A1 input pins. The X9410

compares the serial data stream with the address input

state; a successful compare of both address bits is

required for the X9410 to successfully continue the

command sequence. The A0–A1 inputs can be actively

driven by CMOS input signals or tied to VCC or VSS.

The remaining two bits in the ID byte must be set to 0.

Figure 2. Identification Byte Format

Instruction Byte

The next byte sent to the X9410 contains the

instruction and register pointer information. The four

most signiﬁcant bits are the instruction. The next four

bits point to one of the two pots and when applicable

they point to one of four associated registers. The

format is shown below in Figure 3.

Device Type

Identifier

Device Address

Figure 1. Detailed Potentiometer Block Diagram

Serial Data Path

From Interface

Circuitry

Serial

Bus

Input

Parallel

Bus

Input

Wiper

Counter

INC/DEC

Logic

UP/DN

CLK

Modified SCL

UP/DN

VH/RH

VL/RL

VW/RW

If WCR = 00[H] then VW/RW = VL/RL

If WCR = 3F[H] then VW/RW = VH/RH

(WCR)

(One of Two Arrays)

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