Integrated

Circuit

Systems, Inc.

ICS950908

Preliminary Product Preview

0653A—07/26/04

Pin Configuration

Recommended Application:

VIA Pro266/PN266/CLE266/CM400 chipset for PIII/Tualatin/C3

Processor

Output Features:

•

1 - Pair of differential CPU clocks @ 3.3V (CK408)/

•

1 - Pair of differential open drain CPU clocks (K7)

•

2 - Push pull CPUT_CS clocks @ 2.5V

•

3 - AGP @ 3.3V

•

7 - PCI @ 3.3V

•

1 - 48MHz @ 3.3V fixed

•

1 - 24_48MHz @ 3.3V

•

2 - REF @ 3.3V, 14.318MHz

Key Specifications:

•

CPU_CS - CPUT/C: <±250ps

•

CPU_CS - AGP: <±250ps

•

CPU - DDR/SD: <±250ps

•

PCI - PCI: <500ps

Programmable Timing Control Hub™ for P4™

* Internal 120K pull-up resistor to VDD.

** Internal 120K pull-down resistor to GND.

56-Pin 300-mil SSOP

Frequency Table

*FS0/REF0 1

56 Vtt_PWRGD#**/REF1

GND 2

55 VDDREF

X1 3

54 GND

X2 4

53 CPUCLKT/CPUCLKODT

VDDAGP 5

52 CPUCLKC/CPUCLKODC

*MODE/AGPCLK0 6

51 VDDCPU3.3

*SEL_408/K7/AGPCLK1 7

50 VDDCPU2.5

*(PCI_STOP#)AGPCLK2 8

49 CPUT0_CS

GNDAGP 9

48 CPUT1_CS

**FS1/PCICLK_F 10

47 GND

**SEL_SDR/DDR#/PCICLK1 11

46 FBOUT

*MULTSEL/PCICLK2 12

45 BUF_IN

GNDPCI 13

44 DDRT0/SDRAM0

PCICLK3 14

43 DDRC0/SDRAM1

PCICLK4 15

42 DDRT1/SDRAM2

VDDPCI 16

41 DDRC1/SDRAM3

PCICLK5 17

40 VDD3.3_2.5

*(CLK_STOP#)/PCICLK6 18

39 GND

GND48 19

38 DDRT2/SDRAM4

*FS3/48MHz 20

37 DDRC2/SDRAM5

*FS2/24_48MHz 21

36 DDRT3/SDRAM6

AVDD48 22

35 DDRC3/SDRAM7

VDD 23

34 VDD3.3_2.5

GND 24

33 GND

IREF 25

32 DDRT4/SDRAM8

*(PD#)RESET# 26

31 DDRC4/SDRAM9

SCLK 27

30 DDRT5/SDRAM10

SDATA 28

29 DDRC5/SDRAM11

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Features/Benefits:

•

Programmable output frequency.

•

Programmable output divider ratios.

•

Programmable output rise/fall time.

•

Programmable output skew.

•

Programmable spread percentage for EMI control.

•

Watchdog timer technology to reset system

if system malfunctions.

•

Programmable watch dog safe frequency.

•

Support I

operations.

•

Uses external 14.318MHz crystal.

PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to

change without notice.