16

Integrated

Circuit

Systems, Inc.

ICS952601

0701G—10/13/04

PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power.

When PD# is asserted low all clocks will be driven low before turning off the VCO. In PD# de-assertion all clocks will start

without glitches.

PD#, Power Down

#

N

W

D

R

W

PU

P

C#

U

P

CC

R

S#

C

R

S6

6

V

3I

C

P

/

F

I

C

PT

O

D

/

B

S

UF

E

Re

t

o

N

1l

a

m

r

o

Nl

a

m

r

o

Nl

a

m

r

o

Nl

a

m

r

o

Nz

H

M

6

6z

H

M

3

3z

H

M

8

4z

H

M

8

1

3

.

4

1

0r

o

2

*

f

e

r

I

t

a

o

l

F

t

a

o

l

F2

*

f

e

r

I

t

a

o

l

F

r

o

t

a

o

l

Fw

o

Lw

o

Lw

o

Lw

o

L

Notes:

1. Refer to tristate control of CPU and SRC clocks in section 7.7 for tristate timing and operation.

2. Refer to Control Registers in section 16 for CPU_Stop, SRC_Stop and PwrDwn SMBus tristate control addresses.

PD# should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be

held low on their next high to low transition.

All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register

determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.

When the drive mode but corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at

2 x Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated.

PWRDWN#

CPU, 133MHz

CPU#, 133MHz

SRC, 100MHz

SRC#, 100MHz

3V66, 66MHz

USB, 48MHz

PCI, 33MHz

REF, 14.31818

PD# Assertion