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68HC08M68HC Datasheet(PDF) 97 Page - Motorola, Inc |
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68HC08M68HC Datasheet(HTML) 97 Page - Motorola, Inc |
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97 / 456 page ![]() System Integration Module (SIM) Introduction MC68HC08AZ32A — Rev 1.0 Technical Data MOTOROLA System Integration Module (SIM) 97 Figure 7-1. SIM Block Diagram Table 7-1. SIM I/O Register Summary Register Name Bit 7 6 5 4 3 2 1 Bit 0 Addr. SIM Break Status Register (SBSR) R: R R RRR R BW R$FE00 W: 0 SIM Reset Status Register (SRSR) R: POR PIN COP ILOP ILAD 0 LVI 0 $FE01 W: SIM Break Flag Control Register (SBFCR) BCFE R R R R R R R $FE03 R = Reserved for factory test = Unimplemented STOP/WAIT CLOCK CONTROL POR CONTROL RESET PIN CONTROL MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) SIMOSCEN (TO CGM) CGMOUT (FROM CGM) INTERNAL CLOCKS MASTER RESET CONTROL RESET PIN LOGIC LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) INTERRUPT SOURCES CPU INTERFACE RESET CONTROL SIM COUNTER COP CLOCK CGMXCLK (FROM CGM) ÷ 2 INTERRUPT CONTROL AND PRIORITY DECODE SIM RESET STATUS REGISTER CLOCK GENERATORS Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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