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MSC8101 Datasheet(PDF) 1 Page - Motorola, Inc |
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MSC8101 Datasheet(HTML) 1 Page - Motorola, Inc |
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1 / 104 page ![]() Freescale Semiconductor Technical Data MSC8101 Rev. 16, 11/2004 © Freescale Semiconductor, Inc., 2001, 2004. All rights reserved. MSC8101 Network Digital Signal Processor The Freescale MSC8101 DSP is a very versatile device that integrates the high-performance SC140 four-ALU (arithmetic logic unit) DSP core along with 512 KB of internal memory, a communications processor module (CPM), a 64-bit bus, a very flexible System Integration Unit (SIU), and a 16-channel DMA engine on a single device. With its four-ALU core, the MSC8101 can execute up to four multiply-accumulate (MAC) operations in a single clock cycle. The MSC8101 CPM is a 32- bit RISC-based communications protocol engine that can network to time-division multiplexed (TDM) highways, Ethernet, and asynchronous transfer mode (ATM) backbones. The MSC8101 60x-compatible bus interface facilitates its connection to multi-master system architectures. The very large internal memory, 512 KB, reduces the need for external program and data memories. The MSC8101 offers 1500 DSP MMACS (1200 core and 300 EFCOP) performance using an internal 300 MHz clock with a 1.6 V core and independent 3.3 V input/output (I/O). Figure 1. MSC8101 Block Diagram UTOPIA Other Peripherals MII TDMs CPM PIT System Protection Reset Control Clock Control SIU 8/16-bit Host SC140 Power Management Clock/PLL 64-bit XA Data Bus 128-bit P-Bus 64-bit XB Data Bus Extended Core Interface 64-bit Local Bus 64-bit System Bus Core • • • 3 × FCC 4 × SCC SPI I2C 2 × MCC 2 × SMC Interrupt Timers Baud Rate Parallel I/O Generators Controller Dual Ported RAM Program Sequencer Address Register File Data ALU Register File Address ALU Data ALU 64/32-bit System Bus Interrupts EOnCE™ JTAG 2 × SDMA RISC Interface DMA Engine Bridge Q2PPC Bridge Boot ROM SRAM 512 KB 128-bit QBus MEMC L1 Interface HDI16 MEMC { PIC EFCOP SIC_EXT SIC Interrupts The Freescale MSC8101 16-bit DSP is the first member of the family of DSPs based on the StarCore SC140 DSP core. The MSC8101 is available in three core speed levels: 250, 275, and 300 MHz. What’s New? Rev. 16 includes the following changes: • Changed most REFCLK references to DLLIN in Section 2.7.4. |
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