AD7265

Preliminary Technical Data

THEORY OF OPERATION

CAPACITIVE

DAC

CAPACITIVE

DAC

CONTROL

LOGIC

COMPARATOR

SW3

SW1

A

A

B

B

SW2

CIRCUIT INFORMATION

The AD7265 is a fast, micropower, dual 12-bit, single supply,

A/D converter that operates from a 2.7 V to 5.25 V supply.

When operated from either a 5 V or 3V supply, the AD7265 is

capable of throughput rates of 1 MSPS.

The AD7265 contains two on-chip differential track-and-hold

amplifiers, two successive approximation A/D converters, and a

serial interface with two separate data output pins, and is

housed in a 32-lead LFCSP package, which offers the user

considerable space-saving advantages over alternative solutions.

The serial clock input accesses data from the part but also

provides the clock source for each successive approximation

ADC. The analog input range for the part can be selected to be a

configured as either single ended or differential. The AD7265

has an on-chip 2.5 V reference that can be overdriven if an

external reference is preferred.

Figure 3. ADC Acquisition Phase

When the ADC starts a conversion (Figure 4), SW3 opens and

SW1 and SW2 move to position B, causing the comparator to

become unbalanced. Both inputs are disconnected once the

conversion begins. The control logic and the charge redistribu-

tion DACs are used to add and subtract fixed amounts of charge

from the sampling capacitor arrays to bring the comparator

back into a balanced condition. When the comparator is

rebalanced, the conversion is complete. The control logic

generates the ADC output code. The output impedances of the

otherwise, the two inputs will have different settling times,

resulting in errors.

The AD7265 also features power-down options to allow power

saving between conversions. The power-down feature is

implemented across the standard serial interface, as described in

the Modes of Operation section.

CONVERTER OPERATION

The AD7265 has two successive approximation analog-to-

digital converters, each based around two capacitive DACs.

Figure 3 and Figure 4 show simplified schematics of one of

these ADCs in acquisition and conversion phase, respectively.

The ADC is comprised of control logic, a SAR, and two

capacitive DACs. In Figure 3 (the acquisition phase), SW3, is

closed, SW1 and SW2 are in position A, the comparator is held

in a balanced condition, and the sampling capacitor arrays

acquire the differential signal on the input.

CAPACITIVE

DAC

CAPACITIVE

DAC

CONTROL

LOGIC

COMPARATOR

SW3

SW1

A

A

B

B

SW2

Figure 4. ADC Conversion Phase

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