AD7477AARM datasheet(20/24 Pages) AD

20 / 24 page

REV. C

–20–

AD7476A/AD7477A/AD7478A

To summarize, the values in the SPC register are

FO = 0

FSM = 1

MCM = 1

TXM = 1

The format bit, FO, may be set to 1 to set the word length to

eight bits in order to implement the power-down mode on the

AD7476A/AD7477A/AD7478A.

The connection diagram is shown in Figure 17. It should be noted

that for signal processing applications, it is imperative that the

frame synchronization signal from the TMS320C541 provides

equidistant sampling.

AD7476A/

AD7477A/

AD7478A*

SCLK

SDATA

CLKX

CLKR

FSX

FSR

TMS320C541*

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 17. Interfacing to the TMS320C541

AD7476A/AD7477A/AD7478A to ADSP-218x

The ADSP-218x family of DSPs are interfaced directly to the

AD7476A/AD7477A/AD7478A without any glue logic required.

The SPORT control register should be set up as follows:

TFSW = RFSW = 1, Alternate Framing

INVRFS = INVTFS = 1, Active Low Frame Signal

DTYPE = 00, Right Justify Data

ISCLK = 1, Internal Serial Clock

TFSR = RFSR = 1, Frame Every Word

IRFS = 0, Sets Up RFS as an Input

ITFS = 1, Sets Up TFS as an Output

SLEN = 1111, 16 Bits for the AD7476A

SLEN = 1101, 14 Bits for the AD7477A

SLEN = 1011, 12 Bits for the AD7478A

To implement the power-down mode, SLEN should be set to

0111 to issue an 8-bit SCLK burst. The connection diagram is

shown in Figure 18. The ADSP-218x has the TFS and RFS of

the SPORT tied together, with TFS set as an output and RFS

set as an input. The DSP operates in alternate framing mode, and

the SPORT control register is set up as described. The frame

synchronization signal generated on the TFS is tied to

CS, and,

as with all signal processing applications, equidistant sampling is

necessary. However, in this example, the timer interrupt is used

to control the sampling rate of the ADC and, under certain

conditions, equidistant sampling may not be achieved.

The timer registers, for example, are loaded with a value that will

provide an interrupt at the required sample interval. When an

interrupt is received, a value is transmitted with TFS/DT

(ADC control word). The TFS is used to control the RFS and

thus the reading of data. The frequency of the serial clock is set in

the SCLKDIV register. When the instruction to transmit with

TFS is given, i.e., TX0 = AX0, the state of the SCLK is checked.

The DSP will wait until the SCLK has gone high, low, and high

before transmission will start. If the timer and SCLK values are

chosen such that the instruction to transmit occurs on or near

the rising edge of SCLK, the data may be transmitted or it may

wait until the next clock edge.

For example, the ADSP-2111 has a master clock frequency of

16 MHz. If the SCLKDIV register is loaded with the value 3,

an SCLK of 2 MHz is obtained and eight master clock periods will

elapse for every one SCLK period. If the timer registers are loaded

with the value 803, 100.5 SCLKs will occur between interrupts and

subsequently between transmit instructions. This situation will result

in nonequidistant sampling as the transmit instruction is occurring

on an SCLK edge. If the number of SCLKs between interrupts is a

whole integer figure of N, equidistant sampling will be implemented

by the DSP.

AD7476A/

AD7477A/

AD7478A*

SCLK

SDATA

SCLK

RFS

TFS

ADSP-218x*

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 18. Interfacing to the ADSP-218x

AD7476A/AD7477A/AD7478A to DSP563xx Interface

The connection diagram in Figure 19 shows how the AD7476A/

AD7477A/AD7478A can be connected to the SSI (synchronous

serial interface) of the DSP563xx family of DSPs from Motorola.

The SSI is operated in synchronous and normal mode (SYN = 1

and MOD = 0 in Control Register B, CRB) with internally gener-

ated word frame sync for both Tx and Rx (Bits FSL1 = 0 and

FSL0 = 0 in CRB). Set the word length in Control Register A

(CRA) to 16 by setting Bits WL2 = 0, WL1 = 1, and WL0 = 0

for the AD7476A. The word length for the AD7478A can be set

to 12 bits (WL2 = 0, WL1 = 0, and WL0 = 1). This DSP does not

offer the option for a 14-bit word length, so the AD7477A word

length will be set up to 16 bits, the same as the AD7476A. For the

AD7477A, the conversion process will use 16 SCLK cycles,

with the last two clock periods clocking out two trailing zeros to

fill the 16-bit word.

To implement the power-down mode on the AD7476A/AD7477A/

AD7478A, the word length can be changed to eight bits by setting

Bits WL2 = 0, WL1 = 0, and WL0 = 0 in CRA. The FSP bit in

the CRB register can be set to 1, meaning the frame goes low

and a conversion starts. Likewise, by means of the Bits SCD2,

SCKD, and SHFD in the CRB register, it will be established that

the Pins SC2 (the frame sync signal) and SCK in the serial port

will be configured as outputs and the MSB will be shifted first.

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