LMC1983CIV datasheet(12/14 Pages) NSC

12 / 14 page

Application Information (Continued)

no affect on a respective control. They are necessary to

properly position the data in the LMC1983’s internal data

shift register. Unexpected results may take place if these bits

are not sent.

The LMC1983’s internal data shift register can handle either

a 16-bit word or two 8-bit serial data transmissions. It is the

final 8 bits of data received before the ID line goes high that

are used as the LMC1983 selection and function addresses.

The final eight bits after the ID line returns high are used to

change a function’s operating point. CLK must be stopped

when the final 8 data bits are received. The data stored in the

internal data latch remains unchanged until the ID is pulsed,

signifying the end of data transmission. When ID is pulsed,

the new data in the data shift register is latched into the data

latch and the selected function takes on a new operating

point.

A complete description and more information concerning the

IM Bus is given in the appendix of ITT’s CCU2000

datasheet.

DIGITAL I/O

The LMC1983’s two Digital Input pins, 2 and 3, provide

single-bit communication between a peripheral device and

the controller over the IM Bus. Each pin has an internal

30 k

Ω pull-up resistor. Therefore, these pins should be con-

nected to open collector/drain outputs. The type of informa-

tion that could be received on these lines and retrieved by a

controller include FM stereo pilot indication, power on/off,

Secondary Audio Program (SAP), etc.

According to

Table 1, the logic state of DIGITAL INPUT 1 and

DIGITAL INPUT 2 is latched and can be retrieved over the IM

Bus using the read command (47

H). The single-bit informa-

tion sent on the IM Bus is active low since these lines are in-

ternally pulled high.

LMC1983CIV Datasheet(PDF) 12 Page - National Semiconductor (TI)