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AND8112 Datasheet(PDF) 4 Page - ON Semiconductor |
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AND8112 Datasheet(HTML) 4 Page - ON Semiconductor |
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4 / 12 page ![]() AND8112/D http://onsemi.com 4 Re(d) + t V1(t) u t I1(t) u + 2 LP d(t) 2 TS (eq. 19) where the input impedance depends on the duty−cycle d(t). However, in quasi−resonant converters, the power transfer adjusts by varying the peak current IP which finally imposes the operating frequency. Since by definition ton = d x TS, we can re−arrange equation 9 to reveal TS + ton (N Vg) ) V V (eq. 20) By finally plugging equation 10 and 20 into 19, we obtain a ton−dependent input effective resistance definition: Re(ton) + 2 LP (V ) N Vg) ton V (eq. 21) that Figure 5 portrays: The average input waveforms of the switch can be modeled via the above equivalent network. Figure 5. <V1(t)> <I1(t)> Re(ton) The two−port loss−free network where all the input power trans- forms into output power. Figure 6. <V1(t)> <I1(t)> Re(ton) <P(t)> <I2(t)> <V2(t)> As reference [1] details, the apparent power consumed by Re, Pin, is entirely transmitted to the output since we assume a 100% efficiency. Therefore, equation 19 can be re−written by: t P(t) u+t V1(t) u t I1(t) u+ (eq. 22) t V2(t) u t I2(t) u+ t V1(t) u2 Re(ton) Our switch network can thus modeled according to the so−called loss−free network where all the power developed across an input resistance transfers to the output without any loss (Figure 6) [1]. A More Complex Model Including Parasitic Effects The above simplified model assumes that there are no transient times between the conduction and demagnetization phases. A more precise modelling approach requires that the two following delays Dt1 and Dt2 are taken into account, as highlighted by Figure 7 and 8: Figure 7. The presence of a capacitive node slows−down the VDS rising and makes the drain sinusoidally ring at the core reset … Dt1 Dt2 Core Is Reset! 1. At the end of the ON−time, the power switch opens but the energy transfer to the secondary side does not start immediately. The primary inductor current (IP) that cannot flow through the power switch, charges the surrounding capacitive elements (Ctot) until Ctot voltage exceeds Vg ) V N (eq. 23) At that moment, the secondary diode starts to conduct and current feeds the output capacitor. One can assume that the Ctot charging time ( Dt1) is short enough to consider that the primary inductor current stays equal to IP during this interval. Then, Dt1 is the time necessary to charge the capacitor Ctot with a current IP from zero to Vg ) V N (eq. 24) Dt1 + Ctot Vg ) V N IP , i.e.: |
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