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CS7410 Datasheet(PDF) 19 Page - Cirrus Logic |
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CS7410 Datasheet(HTML) 19 Page - Cirrus Logic |
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19 / 39 page ![]() CS7410 DS553PP1 19 15 0 1 CD_BCK CD_LRCK DATA C2P0 14 13 12 11 10 9 8 7 6 5 4 3 2 Invalid 0 15 0 1 14 13 12 11 10 9 8 7 6 5 4 3 2 Invalid MSB LSB MSB LSB Lower (Left Channel) Upper (Left Channel) Lower (Right Channel) Upper (Right Channel) 32-bit BCK, MSB First, Right Channel Low, C2P0 LSB First, Data latch timing high 15 0 1 CD_BCK CD_LRCK DATA C2P0 14 13 12 11 10 9 8 7 6 5 4 3 2 Invalid 0 15 0 1 14 13 12 11 10 9 8 7 6 5 4 3 2 Invalid MSB LSB MSB LSB Upper (Right Channel) Lower (Right Channel) Upper (Left Channel) Lower (Left Channel) 32-bit BCK, MSB First, Left Channel Low, C2P0 MSB First, Data latch timing low 15 0 1 CD_BCK CD_LRCK DATA C2P0 14 13 12 11 10 9 8 7 6 5 4 3 2 Invalid 0 MSB LSB Lower (Left Channel) Upper (Left Channel) Lower (Right Channel) Upper (Right Channel) 24-bit BCK, MSB First, Right Channel Low, C2P0 MSB First, Data latch timing high Left Channel Right Channel Right Channel Left Channel Left Channel Right Channel 15 0 1 14 13 12 11 10 9 8 7 6 5 4 3 2 Invalid MSB LSB 15 14 13 12 11 10 9 8 7 6 5 Invalid MSB Upper (Left Channel) Left Channel CD_BCK CD_LRCK DATA C2P0 Invalid 0 LSB MSB Lower (Left Channel) Upper (Left Channel) Lower (Right Channel) Upper (Right Channel) 24-bit BCK, LSB First, Right Channel Low, C2P0 MSB First, Data latch timing low Left Channel Right Channel Invalid LSB MSB Invalid LSB Upper (Left Channel) Left Channel 0 15 1 14 13 12 11 10 9 8 7 6 5 4 3 2 0 15 1 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 10 9 8 7 6 5 4 3 2 15 0 1 CD_BCK CD_LRCK DATA 14 13 12 11 10 9 8 7 6 5 4 3 2 Invalid 0 MSB LSB 24-bit BCK, MSB First, Right Channel Low, Data latch timing high (Note: no C2P0 for this format) Left Channel Right Channel 15 0 1 14 13 12 11 10 9 8 7 6 5 4 3 2 Invalid MSB LSB 15 14 13 12 11 10 9 8 7 6 5 Invalid MSB Left Channel 15 0 1 CD_BCK CD_LRCK DATA C2P0 14 13 12 11 10 9 8 7 6 5 4 3 2 0 MSB LSB Lower (Left Channel) Upper (Left Channel) Lower (Right Channel) Upper (Right Channel) 16-bit BCK, MSB First, Left Channel Low, C2P0 LSB First, Data latch timing high Left Channel Right Channel 15 0 1 14 13 12 11 10 9 8 7 6 5 4 3 2 MSB LSB 15 0 1 14 13 12 11 10 9 8 7 6 5 4 3 2 MSB LSB Lower (Left Channel) Upper (Left Channel) Lower (Right Channel) Upper (Right Channel) Left Channel Right Channel 15 0 1 14 13 12 11 10 9 8 7 6 5 4 3 2 MSB LSB 15 14 13 MSB Figure 14. CD Interface Timing Diagrams |
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