MB9B100 Series

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FEATURES

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32-bit ARM Cortex-M3 Core

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Processor version: r2p0

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Up to 80MHz Frequency Operation

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Memory Protection Unit (MPU): improve the reliability of an embedded system

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Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48

peripheral interrupts and 16 priority levels

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24-bit System timer (Sys Tick): System timer for OS task management

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On-chip Memories

[Flash memory]

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Up to 512 Kbyte

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Read cycle: 0wait-cycle@up to 60MHz, 2wait-cycle* above

*: Instruction pre-fetch buffer is included. So when CPU access continuously, it becomes 0wait-cycle

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Security function for code protection

[SRAM]

MB9B100 Series contain a total of up to 64Kbyte on-chip SRAM memories. This is composed of two

independent SRAM for CPU and DMA Controller can process simultaneously.

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Up to 32 Kbyte SRAM for high-performance CPU

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Up to 32 Kbyte SRAM for CPU/DMA Controller

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External Bus Interface

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Supports SRAM, NOR& NAND Flash device

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Up to 8 chip selects

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8/16-bit Data width

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Up to 25-bit Address bit

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Multi-function Serial Interface (Max. 8channels)

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4 channels with 16-byte FIFO (ch.4-ch.7), 4 channels without FIFO (ch.0-ch.3)

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Operation mode is selectable from the followings for each channel.

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UART

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CSIO

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LIN

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[UART]

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Full-duplex double buffer

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Selection with or without parity supported

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Built-in dedicated baud rate generator

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External clock available as a serial clock

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Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)

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Various error detect functions available (parity errors, framing errors, and overrun errors)

[CSIO]

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Full-duplex double buffer

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Built-in dedicated baud rate generator

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Overrun error detect function available

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FUJITSU SEMICONDUCTOR CONFIDENTIAL

r2.1

DS706-00007-1v0-E