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LMV7219 Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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LMV7219 Datasheet(HTML) 8 Page - National Semiconductor (TI) |
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8 / 12 page ![]() Typical Performance Characteristics Unless otherwise specified, V S = 5V, CL = 10pF, TA = 25˚C (Continued) Application Section LMV7219 is a single supply comparator with internal hyster- esis, 7ns of propagation delay and only 1.1mA of supply cur- rent. The LMV7219 has a typical input common mode voltage range of −0.2V below the ground to 1V below V cc. The differ- ential input stage is a pair of PNP transistors, therefore, the input bias current flows out of the device. If either of the input signals falls below the negative common mode limit, the parasitic PN junction formed by the substrate and the base of the PNP will turn on, resulting in an increase of input bias current. If one of the inputs goes above the positive common mode limit, the output will still maintain the correct logic level as long as the other input stays within the common mode range. However, the propagation delay will increase. When both in- puts are outside the common mode voltage range, current saturation occurs in the input stage, and the output becomes unpredictable. The propagation delay does not increase significantly with large differential input voltages. However, large differential voltages greater than the supply voltage should be avoided to prevent damages to the input stage. The LMV7219 has a push pull output. When the output switches, there is a direct path between V cc and ground, causing high output sinking or sourcing current during the transition. After the transition, the output current decreases and the supply current settles back to about 1.1mA at 5V, thus conserving power consumption. Most high-speed comparators oscillate when the voltage of one of the inputs is close to or equal to the voltage on the other input due to noise or undesirable feedback. The LMV7219 have 7mV of internal hysteresis to counter para- sitic effects and noise. The hysteresis does not change sig- nificantly with the supply voltages and the common mode in- put voltages as reflected in the specification table. The internal hysteresis creates two trip points, one for the rising input voltage and one for the falling input voltage. The difference between the trip points is the hysteresis. With in- ternal hysteresis, when the comparator’s input voltages are equal, the hysteresis effectively causes one comparator- input voltage to move quickly past the other, thus taking the input out of the region where oscillation occurs. Standard comparators require hysteresis to be added with external re- sistors. The fixed internal hysteresis eliminates these resistors. Additional Hysteresis If additional hysteresis is desired, this can be done with the addition of three resistors using positive feedback, as shown in Figure 2. The positive feedback method slows the com- parator response time. Calculate the resistor values as fol- lows: 1) Select R3. The current through R3 should be greater than the input bias current to minimize errors. The current through R3 (I F) at the trip point is (VREF -VOUT) /R3. Consider the two possible output states when solving for R3, and use the smaller of the two resulting resistor values. The two formulas are: R3=V REF/IF (when V OUT =0) R3=V CC -VREF /IF (V OUT =VCC) 2) Choose a hysteresis band required (V HB). 3) Calculate R1, where R1 = R3 X(V HB/VCC) 4) Choose the trip point for V IN rising. This is the threshold voltage (V THR) at which the comparator switches from low to high as V IN rises about the trip point. 5) Calculate R2 as follows: 6) Verify the trip voltage and hysteresis as follows: Propagation Delay (t PD+) DS101054-17 DS101054-18 FIGURE 1. Input and Output Waveforms, Non-Inverting Input Varied www.national.com 8 |
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