2.0

2.2.2

MAIN_R REGISTER

If the Control Bits (CTL [1:0]) are 1 0 when LE transitions high, data is transferred from the 18-bit shift register into a latch which

sets the Main PLL 12-bit R counter divide ratio and various control functions. The divide ratio is programmed using the bits

MAIN_R_CNTR as shown in table 2.2.3. The divider ratio must be

≥ 2. The charge pump control word (CP_WORD[3:0] ) sets the

charge pump gain and the phase detector polarity as detailed in 2.4.

First Bit

SHIFT REGISTER BIT LOCATION

Last Bit

17

16

15

14

13

12

11

10

9876543210

MAIN_R

CP_WORD[3:0]

MAIN_R_CNTR[11:0]

1

0

2.2.3

12-Bit Programmable Main and Auxiliary Reference Divider Ratio

(MAIN/AUX R Counter)

MAIN_R_CNTR/AUX_R_CNTR

Divide Ratio

11

10

9876543210

2

000000000010

3

000000000011

•

••••••••••••

4,095

111111111111

Note 7: Legal divide ratio: 2 to 4,095.

2.3

PROGRAMMABLE FEEDBACK (N) DIVIDERS

2.3.1

AUX_N Register

If the Control Bits ( CTL[1:0]) are 0 1 when LE transitions high, data is transferred from the 18-bit shift register into the AUX_N

register latch which sets the Aux PLL 16-bit programmable N counter value. The AUX_N counter is a 16-bit counter which is fully

programmable from 240 to 65,535 for 1.1 GHz option or from 56 to 32,767 for 500 MHz option. The AUX_N register consists of

the 4-bit swallow counter (AUX_A_CNTR), the 12-bit programmable counter (AUX_B_CNTR). Serial data format is shown below.

The divide ratio (AUX_N_CNTR [13:0]) must be

≥ 240 (1.1 GHz option) or ≥ 56 (500 MHz option) for a continuous divide range.

The Aux PLL N divide ratio is programmed using the bits AUX_A_CNTR, AUX_B_CNTR as shown in tables 2.3.2.

First Bit

SHIFT REGISTER BIT LOCATION

Last Bit

17

16

15

14

13

12

11

10

9876543210

AUX_N

AUX_B_CNTR[11:0]

AUX_A_CNTR[3:0]

0

1

2.3.2

4-BIT Swallow Counter Divide Ratio (Aux A COUNTER)

1.1 GHz option

Swallow

AUX_A_CNTR

Count

(A)

3

2

1

0

0

0

000

1

0

001

•

•

•••

15

1

111

Note 8: Swallow Counter Value: 0 to 15

500 MHz option

Swallow

AUX_A_CNTR

Count

(A)

3210

0

X

000

1

X

001

•

••••

7

X

111

Note 9: Swallow Counter Value: 0 to 7

X = Don’t Care condition

2.3.3

12-BIT Programmable Counter Divide Ratio (Aux B COUNTER)

AUX_B_CNTR

Divide Ratio

11

10

9876543210

3

000000000011

4

000000000100

•

••••••••••••

4,095

111111111111

Note 10: Divide ratio: 3 to 4,095 (Divide ratios less than 3 are prohibited)

AUX_B_CNTR

≥ AUX_A_CNTR.

See section 2.3.7 for calculation of VCO output frequency.

7

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