PROGRAMMABLE DIVIDER (N COUNTER)

The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter) If the Control

Bit (last bit shifted into the Data Register) is LOW data is transferred from the 19-bit shift register into a 7-bit latch which sets

the 7-bit Swallow (A) Counter and an 11-bit latch which sets the 11-bit programmable (B) Counter Serial data format is shown

below

TLW12459 – 15

Note

S8 to S18 Programmable counter divide ratio control bits (3 to 2047)

7-BIT SWALLOW COUNTER DIVIDE RATIO

(A COUNTER)

Divide

N

7

N

6

N

5

N

4

N

3

N

2

N

1

Ratio

A

0

0

000000

1

0

000001

#

#

######

127

1111111

Note

Divide ratio 0 to 127

11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO

(B COUNTER)

Divide

18

N

17

N

16

N

15

N

14

N

13

N

12

N

11

N

10

NN

9

N

8

Ratio

B

3

000000000

1

1

4

000000001

0

0

#

#########

#

#

2047

1

1

1

1

1

1

1

1

1

1

1

Note

Divide ratio 3 to 2047 (Divide ratios less than 3 are prohibited)

PULSE SWALLOW FUNCTION

lator (VCO)

B

Preset divide ratio of binary 11-bit programmable

counter (3 to 2047)

A

Preset divide ratio of binary 7-bit swallow counter

oscillator

R

Preset divide ratio of binary 14-bit programmable ref-

erence counter (3 to 16383)

P

Preset modulus of dual modulus prescaler (64 or 128)

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