M844 Rev 1.3

Revision 12Nov2003

Integ r ated Circuit Systems , Inc. ● Comm unication s Modules ● ww w. i c s t . c o m ● tel (508) 852-5400

Integrated

Circuit

Systems, Inc.

Product Br ief

M844

The M844 Multi-Rate Clock Recovery module provides

low jitter clock recovery from NRZ or RZ input data

formats. Four data rates are digitally selectable: 9.953,

10.3125, 10.664, or 10.709Gb/s. Incoming data is first

amplified by a limiting amplifier. The data is then both:

a) provided as the module’s unretimed data output, and

b) applied to the clock recovery circuitry. A Phase

Locked Loop (PLL) incorporates frequency multipliers

and a SAW-based Voltage Control SAW Oscillator

(VCSO) to minimize clock jitter. The VCSO provides the

high Q, low noise, and high stability needed for the

narrow bandwidth PLL operation. Micro-strip bandpass

filters are used to produce sinusodal clock output with

low harmonic and sub-harmonic distortion.

10.664, or 10.709Gb/s

peak-to-peak max

data output

Example Input/Output Frequency Combinations

Operating

Data Rate

(Gb/s)

Clock Output Freq

(GHz)

Application

OC-192

OC-48

9.9530

9.9530

2.488

OC-192

10.3125

10.3125

2.577

10.6640

10.6640

2.666

10.7090

10.7090

2.677

M844

CONT 2

CONT 1

ALM

GND

GND

VCC +5V

Din

1/4Cout

Cout

Dout

VEE -5V

M844

DATA_IN

CLK_OUT

Rate

Select

2x

Frequency

Multiplier

4x

Frequency

Multiplier

Lim

Amp

RF

Amp

DATA_OUT

Phase Detector

RF

Amp

RF

Amp

Op-

Amp

RF

Amp

1/4CLK_OUT

RF

Amp

Pwr

Div

SAW Delay Lines 1 - 4

SP4T

SW

SP4T

SW

Phase

Shifter

Pwr

Div

2x

Frequency

Multiplier

Pwr

Div

M844 Multi-Rate Clock Recovery