LMX2335TM datasheet(11/18 Pages) NSC

11 / 18 page

Functional Description (Continued)

Note 9: When the FoLD output is disabled it is actively pulled to a low logic state.

Note 10: Lock detect output provided to indicate when the VCO frequency is in “lock”. When the loop is locked and a lock detect mode is selected, the pins output

is HIGH, with narrow pulses LOW. In the RF1/RF2 lock detect mode a locked condition is indicated when RF2 and RF1 are both locked.

Note 11: The Fastlock mode utilized the FoLD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation of Fastlock

occurs whenever the RF loop’s Icpo magnitude bit #17 is selected HIGH (while the #19 and #20 mode bits are set for Fastlock).

Note 12: The Counter Reset mode bits R19 and R20 when activated reset all counters. Upon removal of the Reset bits the N counter resumes counting in “close”

alignment with the R counter. (The maximum error is one prescaler cycle). If the Reset bits are activated the R counter is also forced to Reset, allowing smooth ac-

quisition upon powering up.

SERIAL DATA INPUT TIMING

PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS

DS012332-8

Notes: Parenthesis data indicates programmable reference divider data.

Data shifted into register on clock rising edge.

Data is shifted in MSB first.

Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6V/ns with

amplitudes of 2.2V @ VCC = 2.7V and 2.6V @ VCC = 5.5V.

DS012332-9

Notes: Phase difference detection range: −2

π to +2π

The minimum width pump up and pump down current pulses occur at the Do pin when the loop is locked.

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