ADNS-5070 datasheet(21/41 Pages) AVAGO

21 / 41 page

Notes on Power-up and the Serial Port

The sequence in which VDD, SCLK and SDIO are set during

power-up can affect the operation of the serial port. The

diagram below shows what can happen shortly after

Figure 25. Power-up serial port sequence

This diagram shows the VDD rising to valid levels, at some

point the microcontroller starts it’s program, sets the

SCLK and SDIO lines to be outputs, and sets them high.

Then, the microcontroller waits to ensure the ADNS-5070

has powered up and is ready to communicate. The mi-

croprocessor then tries to read from location 0x41, Status

receives this value, then it knows the communication to

the ADNS-5070 is operational.

The problem occurs if the ADNS-5070 powers up before

the microprocessor sets the SCLK and SDIO lines to be

outputs and high. The ADNS-5070 sees the raising of the

SCLK as a valid rising edge, and clocks in the state of the

SDIO as the first bit of the address (sets either a read or a

write, depending upon the state).

In the case of a SDIO low, a read operation will start. When

the microprocessor actually begins to send the address,

the ADNS-5070 already has the first bit of an address.

When the seventh bit is sent by the microprocessor, the

ADNS-5070 has a valid address, and drives the SDIO line

high within 250 ns (see detail “A” in Figure 18 and Figure

19). This results in a bus fight for SDIO. Since the address

is wrong, the data sent back would be incorrect.

In the case of a SDIO high, a write operation will start. The

address and data will be out of synchronization, causing

the wrong data written to the wrong address.

Figure 26. Power up serial port timer sequence

power-up when the microprocessor tries to read data

from the serial port.

Data = 0x0b010XXXXX

Address = 0x41

SCLK

SDIO

VDD

Problem Area

SCLK

SDIO

VDD

Data = 0x0b010XXXXX

Address = 0x41

>tSPTT

Don't Care State

Solution

One way to solve the problem is by waiting for the serial

port timer to time out.

1. Serial Port Timer Timeout

ADNS-5070 Datasheet(PDF) 21 Page - AVAGO TECHNOLOGIES LIMITED

ADNS-5070 Datasheet(HTML) 21 Page - AVAGO TECHNOLOGIES LIMITED

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

Datasheet Download

Link URL