4.1.2 3-BIT IF SWALLOW COUNTER DIVIDE RATIO (IF A COUNTER)

(IF_N[2]−[4])

Swallow Count

IF_NA_CNTR

(A)

2

1

0

0

000

1

001

-

---

7

111

Note: Swallow Counter Value: 0 to 7

IF_NB_CNTR

≥ IF_NA_CNTR

Minimum continuous count = 56 ( A=0, B=7)

4.1.3 12-BIT IF PROGRAMMABLE COUNTER DIVIDE RATIO (IF B COUNTER)

(IF_N[5]-[16])

IF_NB_CNTR

Divide Ratio

11

109876543210

3

0

0

0000000011

4

0

0

0000000100

-

-

-

----------

4,095

1

1

1111111111

Note: Divide ratio: 3 to 4095 (Divide ratios less than 3 are prohibited)

IF_NB_CNTR

≥ IF_NA_CNTR

N divider continuous integer divide ratio 56 to 32,767.

4.2 RF_N Register

If the control bits (CTL[2:0]) are 11, data is transferred from the 24-bit shift register into the RF_N register latch which sets the RF

PLL 19 bit programmable N counter register and various control functions. The RF N counter consists of the 5-bit swallow counter

(A counter) the 10 bit programmable counter (B counter), and 4 bit fractional counter. Serial data format is shown below. The

divide ratio (RF_NB_CNTR) must be

≥3, and must be ≥ the swallow counter value + 2; RF_NB_CNTR≥ ( RF_NA_CNTR+2).

MSB

LSB

RF_CTL_WORD [2:0]

RF_NB_CNTR [9:0]

RF_NA_CNTR [4:0]

FRAC_CONT [3:0]

1

1

23

21

20

11

10

6

5

2

1

0

4.2.1.1 RF_CTL_WORD

(RF_N[21]-[23])

MSB

LSB

RF_CNT_RST

PWDN_RF

PRESC_SEL

4.2.1.2 RF/IF Control Word Truth Table

BIT

FUNCTION

0

1

IF_CNT_RST/RF_CNT_RST

IF/RF counter reset

Normal Operation

Reset

PWDN_IF/PWDN_RF

IF/RF power down

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PWDN_MODE

Power down mode select

Asynchronous power down

Synchronous power down

PRESC

LMX2350

Prescaler Modulus select

16/17

(0.5 to 1.2 GHz operation)

32/33

(1.2 to 2.5 GHz operation)

LMX2352

8/9

(0.25 to 0.5 GHz operation)

16/17

(0.5 to 1.2 GHz operation)

The Counter Reset enable bit when activated allows the

reset of both N and R counters. Upon powering up, the N

counter resumes counting in ’close’ alignment with the R

counter (the maximum error is one prescaler cycle).

Activation of the PLL power down bits result in the disabling

of the respective N counter divider and de-biasing of its

respective fin inputs (to a high impedance state). The re-

spective R counter functionality also becomes disabled

when the power down bit is activated. The OSCin pin reverts

to a high impedance state when both RF and IF power down

bits are asserted. Power down forces the respective charge

pump and phase comparator logic to a TRI-STATE condition.

The MICROWIRE control register remains active and ca-

pable of loading and latching in data during all of the power

down modes.

Both synchronous and asynchronous power down modes

are available with the LMX2350 family in order to adapt to

different types of applications. The power down mode bit

IF_N[21] is used to select between synchronous and asyn-

chronous power down. The MICROWIRE control register

remains active and capable of loading and latching in data

during all of the power down modes.

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