LP2975 datasheet(15/19 Pages) NSC

15 / 19 page

Application Hints (Continued)

that when the total phase shift at 0 dB reaches (or gets close

to) −180˚, oscillations will result. Therefore, it can be seen

that at least two poles in the gain curve are required to

cause instability.

ZERO: A zero has an effect that is exactly

opposite to a pole.

A zero will add a maximum +90˚ of phase lead (defined as

positive phase shift). Also, a zero causes the slope of the

gain curve to increase by an additional +20 dB/decade (see

graph

EFFECTS OF A SINGLE ZERO).

TOTAL PHASE SHIFT: The actual test of whether or not a

regulator is stable is the amount of phase shift that is present

when the gain curve crosses the 0 dB axis (the frequency

where this occurs was previously defined as f

c).

The phase shift at f

c can be estimated by looking at all of the

poles and zeroes on the Bode plot and adding up the contri-

butions of phase lag and lead from each one. As shown in

the graphs, most of the phase lag (or lead) contributed by a

pole (or zero) occurs within one decade of the frequency of

the pole (or zero).

In general, a phase margin (defined as the difference be-

tween the total phase shift and −180˚) of at least 20˚ to 30˚

is required for a stable loop.

STABILITY ANALYSIS OF TYPICAL APPLICATIONS

The first application to be analyzed is a fixed-output voltage

regulator with no feed-forward capacitor (see graph

STABLE

PLOT WITHOUT FEED-FORWARD).

In this example, the value of C

OUT is selected so that the

pole formed by C

OUT and RL (previously defined as fp)isset

at 200 Hz. The ESR of C

OUT is selected so that zero formed

by the ESR and C

OUT (defined as fz) is set at 5 kHz (these

selections follow the general guidelines stated previously in

this document). Note that the gate capacitance is assumed

to be moderate, with the pole formed by the C

GATE (defined

as f

pg) occurring at 100 kHz.

To estimate the total phase margin, the individual phase shift

contributions of each pole and zero will be calculated assum-

ing f

p = 200 Hz, fz = 5 kHz, fc = 10 kHz and fpg = 100 kHz:

Controller pole shift = −90˚

p shift = −arctan (10k/200) = −89˚

z shift = arctan (10k/5k) = +63˚

pg shift = −arctan (10k/100k) = −6˚

Summing the four numbers, the estimate for the total phase

shift is −122˚, which corresponds to a phase margin of 58˚.

This application is stable, but could be improved by using a

feed-forward capacitor (see next section).

EFFECT OF FEED-FORWARD: The example previously

used will be continued with the addition of a feed-forward ca-

pacitor C

F (see graph IMPROVED PHASE MARGIN WITH

FEED-FORWARD). The zero formed by C

F (previously de-

fined as f

zf) is set at 10 kHz and the pole formed by CF (pre-

viously defined as f

pf) is set at 40 kHz (the 4X ratio of fpf/fzf

corresponds to V

OUT = 5V).

Effects of a Single Pole

DS100034-25

Effects of a Single Zero

DS100034-26

Stable Plot without Feed-Forward

DS100034-27

LP2975 Datasheet(PDF) 15 Page - National Semiconductor (TI)

LP2975 Datasheet(HTML) 15 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Datasheet Download

Link URL