SI9130 datasheet(13/13 Pages) VISHAY

13 / 13 page

Si9130

Vishay Siliconix

Document Number: 70190

S-40805—Rev. F, 26-Apr-04

www.vishay.com

DESIGN CONSIDERATIONS

Inductor Design

Three specifications are required for inductor design: inductance

(L), peak inductor current (ILPEAK), and coil resistance (RL). The

equation for computing inductance is:

L +

VOUT VIN(MAX)–VOUT

VIN(MAX) (f) IOUT (LIR)

Where:

VOUT = Output voltage (3.3 V or 5 V);

VIN(MAX) = Maximum input voltage (V);

f =

Switching frequency, normally

300 kHz;

IOUT = Maximum dc load current (A);

LIR = Ratio of inductor pea-to-peak ac current to

average dc load current, typically 0.3.

When LIR is higher, smaller inductance values are acceptable, at

the expense of increased ripple and higher losses.

The peak inductor current (ILPEAK) is equal to the steady-state

load current (IOUT) plus one half of the peak-to-peak ac current

(ILPP). Typically, a designer will select the ac inductor current to be

30% of the steady-state current, which gives ILPEAK equal to 1.15

times IOUT.

The equation for computing peak inductor current is:

ILPEAK + IOUT )

VOUT VIN(MAX)–VOUT

(2)(f)(L) VIN(MAX)

OUTPUT CAPACITORS

The output capacitors determine loop stability and ripple voltage

at the output. In order to maintain stability, minimum capacitance

and maximum ESR requirements must be met according to the

following equations:

CF u

VREF

VOUT RCS (2)(p)(GPWP)

Where:

CF = Output filter capacitance (F)

VREF = Reference voltage, 3.3 V;

VOUT = Output voltage, 3.3 V or 5 V;

RCS = Sense resistor (W);

GBWP = Gain-bandwidth product, 60 kHz;

ESRCF = Output filter capacitor ESR (W).

ESRCF t

VOUT RCS

VREF

and,

Both minimum capacitance and maximum ESR requirements

must be met. In order to get the low ESR, a capacitance value two

to three times greater than the required minimum may be

necessary.

The equation for output ripple in continuous current mode is:

VOUT(RPL) + ILPP(MAX)

ESRCF )

CF)

The equations for capacitive and resistive components of the

ripple in pulse-skipping mode are:

VOUT(RPL)(C) +

if VOUT(RPL)(R) < 0.5 VOUT(RPL)(C),

then VOUT(RPL) = VOUT(RPL)(C),

otherwise, VOUT(RPL) = VOUT(RPL)(C) +

VOUT(RPL)(R).

The total ripple, VOUT(RPL), can be approximated

as follows:

(4) 10–4 (L)

RCS2 CF

VOUT

)

VIN–VOUT

Volts

VOUT(RPL)(R) +

(0.02) ESRCF

RCS

Volts

Lower Voltage Input

The application circuit shown here can be easily modified to work

with 5.5-V to 12-V input voltages. Oscillation frequency should be

set at 200 kHz and increase the output capacitance to 660 mF on

the 5-V output to maintain stable performance up to 2 A of load

current. Operation on the 3.3-V supply will not be affected by this

reduced input voltage.

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