UPD72874 datasheet(13/40 Pages) NEC

13 / 40 page

Preliminary Data Sheet S15306EJ2V0DS

µµµµPD72874

2. PHY REGISTERS

2.1 Complete Structure for PHY Registers

Figure 2-1. Complete Structure of PHY Registers

0000

Physical_ID

0001

RHB

IBR

Gap_count

0010

Extended (7)

Reserved

Total_ports

0011

Max_speed

Reserved

Delay

0100

Link_active

Contender

Jitter

Pwr_class

0101

Watchdog

ISBR

Loop

Pwr_fail

Timeout

Port_event

Enab_accel

Enab_multi

0110

Reserved

0111

Page_select

Reserved

Port_select

1000

Register0 (page_select)

1001

Register1 (page_select)

1010

Register2 (page_select)

1011

Register3 (page_select)

1100

Register4 (page_select)

1101

Register5 (page_select)

1110

Register6 (page_select)

1111

Register7 (page_select)

Table 2-1. Bit Field Description (1/3)

Field

Size

R/W

Reset value

Description

Physical_ID

000000

Physical_ID value selected from Self_ID period.

If this bit is 1, the node is root.

1: Root

0: Not root

Cable power status.

1: Cable power on

0: Cable power off

RHB

R/W

Root Hold -off bit. If 1, becomes root at the bus reset.

IBR

R/W

Initiate bus reset.

Setting to 1 begins a long bus reset.

Long bus reset signal duration: 166

µsec.

Returns to 0 at the beginning of bus reset.

Gap_count

R/W

111111

Gap count value.

It is updated by the changes of transmitting and receiving the PHY

configuration packet Tx/Rx.

The value is maintained after first bus reset.

After the second bus reset it returns to reset value.

Extended

111

Shows the extended register map.

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