Block Diagram

Applications Information

7-segment displays with minimal interface with the display

and data source. Serial data transfer from the data source to

the display driver is accomplished with 2 signals, serial Data

and Clock. Using a format of a leading

″1″ followed by the 33

data bits and 2 trailing don’t care bits, allows data transfer

without the need of an additional Data Load signal. Since the

MM145453 does not contain a character generator, the for-

matting of the segment information must be done prior to in-

putting the data to the MM145453. The transfer of the 33

data bits is complete at the falling edge of the 36th clock

cycle, thus providing non-multiplexed, direct drive to the dis-

play. Outputs change only if the serial data bits differ from

the previous time.

Figure 3 shows the data input format. A single start bit of logi-

cal ’1’ precedes the 33 bits of segment data for a total of 34

bits that need to be defined and clocked in. After the 34 bits

are clocked in, 2 additional clock cycles are required. At the

36th clock cycle an internal LOAD signal is generated syn-

chronously with the rising edge of the Clock In signal, which

loads the 33 bits of segment data in the shift register into the

latches. At the falling edge of the 36th clock cycle an internal

RESET signal is generated which clears all the shift registers

for the next set of data. The shift registers are static master-

slave configuration. There is no clear for the master portion

of the first shift register, thus allowing continuous operation.

The data during the 35th and 36th clock cycles is

″don’t

care

″, but setting data to logical ’0’ for these two clock cycles

is the preferred format.

The data input bits map directly to the segment output pins

and the display. The MM145453 does not have any format

restrictions, as all outputs are controllable.

The MM145453 has an internal oscillator which can gener-

ate the required clock signal to drive the LCD back plane.

The frequency of the internal oscillator is set by a pull-up re-

sistor (R

a capacitor (C

Ground. Due to the current sink limitations of the OSC_IN

circuitry, the lowest recommended resistor value for setting

the oscillator frequency is 9k

Ω. It will typically take 2 to 4 RC

time constants to charge the OSC_IN pin from near 0V to

within 1V of V

the OSC_IN circuitry. An approximate calculation of f

f

AR

value of 0.01µF and a V

typical oscillator frequency ( f

f

BP_OUT pin. For this example the approximate BP_OUT

frequency will be f

DS101283-2

FIGURE 1.

DS101283-3

FIGURE 2.

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