ADC10831 datasheet(19/30 Pages) NSC

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Pin Descriptions

CLK

The clock applied to this input controls the suc-

cessive approximation conversion time interval

the acquisition time and the rate at which the

serial data exchange occurs The rising edge

loads the information on the DI pin into the mul-

tiplexer address shift register This address con-

trols which channel of the analog input multi-

plexer (MUX) is selected The falling edge shifts

the data resulting from the AD conversion out

on DO CS enables or disables the above func-

tions The clock frequency applied to this input

can be between 5 kHz and 3 MHz

This is the serial data input pin The data applied

to this pln is shifted by CLK into the multiplexer

address register Tables I through III show the

multiplexer address assignment

The data output pin The AD conversion result

(DB0-SIGN) are clocked out by the falling edge

of CLK on this pin

This is the chip select input pin When a logic

low is applied to this pin the rising edge of CLK

shifts the data on DI into the address register

This low also brings DO out of TRI-STATE after

a conversion has been completed

This is the power down input pin When a logic

high is applied to this pin the AD is powered

down When a low is applied the AD is pow-

ered up

SARS

This is the successive approximation register

status output pin When CS is high this pin is in

TRI-STATE With CS low this pin is active high

when a conversion is in progress and active low

at all other times

CH0 – CH7 These are the analog inputs of the MUX A

channel input is selected by the address infor-

mation at the DI pin which is loaded on the ris-

ing edge of CLK into the address register (see

Tables I – III)

The voltage applied to these inputs should not

exceed AVa or go below Vb by more than

50 mV Exceeding this range on an unselected

channel will corrupt the reading of a selected

channel

COM

This pin is another analog input When the ana-

log multiplexer is single ended this input serves

as the zero reference level for inputs CH0 – CH7

(see Tables I-III) COM can serve as a ‘‘pseudo

ground’’ that has an input voltage range of AVa

50 mV to Vb b 50 mV In most cases COM

will be grounded When the MUX is set in the

differential pairs mode COM is not used and

may be grounded

VREFa

This is the positive analog voltage reference in-

put In order to malntaln accuracy the voltage

range VREF (VREF e VREFa –VREFb)is

05 VDC to 50 VDC and the voltage at VREFa

cannot exceed AVa a50 mV

VREFb

The negative voltage reference input In order to

maintain accuracy the voltage at this pin must

not go below GND b 50 mV or exceed AVa

50 mV VREFb must always be less than

VREFa

AVa

DVa

These are the analog and digital positive power

supply pins These pins should be tied to the

same power supply and bypassed separately

The operating voltage range of AVa and DVa

is 45 VDC to 55 VDC

This is the negative analog supply pin The oper-

ating voltage range of Vb is b45V to b55V

This supply pin needs to be bypassed with

01 mF ceramic and 10 mF tantalum capacitors

to the system analog ground

DGND

This is the digital ground pin

AGND

This is the analog ground pin

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