L7985ATR datasheet(20/42 Pages) STMICROELECTRONICS

20 / 42 page

Application information

L7985

20/42

DocID022446 Rev 7

As seen in Section 5.3 on page 11, two different kinds of network can compensate the loop.

In the following two paragraphs the guidelines to select the type II and type III compensation

network are illustrated.

6.4.1

Type III compensation network

The methodology to stabilize the loop consists of placing two zeroes to compensate the

effect of the LC double pole, therefore increasing phase margin; then, to place one pole in

the origin to minimize the DC error on regulated output voltage; and finally, to place other

poles far from the zero dB frequency.

If the equivalent series resistance (ESR) of the output capacitor introduces a zero with

a frequency higher than the desired bandwidth (that is: 2

ESR COUT < 1 / BW), the type

III compensation network is needed. Multi-layer ceramic capacitors (MLCC) have very low

ESR (< 1 m

), with very high frequency zero, so a type III network is adopted to

compensate the loop.

In Figure 10 the type III compensation network is shown. This network introduces two

zeroes (fZ1, fZ2) and three poles (fP0, fP1, fP2). They are expressed as:

Equation 22

Equation 23

Figure 10. Type III compensation network

In Figure 11 the Bode diagram of the PWM and LC filter transfer function (GPW0 · GLC(f))

and the open-loop gain (GLOOP(f) = GPW0 · GLC(f) · GTYPEIII(f)) are shown.

fZ1

 C

R1 R3





------------------------------------------------

fZ2

 R

4 C4



------------------------------



fP0 0

fP1

 R

3 C3



------------------------------

fP2

 R

C4 C5



C4 C5

--------------------



--------------------------------------------



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