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LT1310

1310f

SHDN

SHUTDOWN

GND

1.255V

REF

RAMP

GEN.

EXPOSED

PAD

PHASE

DETECTOR

VCO

–

PLL-LPF

SYNC

0.024

Ω

1310 BD

6, 7

×5

To understand operation, refer to the Block Diagram. The

LT1310 contains a boost switching regulator that can be

phase locked to an external synchronizing signal. The

boost regulator uses current mode control and contains a

1.5A NPN power transistor. This type of control uses two

feedback loops. The main control loop sets output voltage

and operates as follows: a load step causes VOUT and the

FB voltage to be slightly perturbed. The error amplifier A1

responds to this change in FB by driving the VC pin either

higher or lower. Because switch current is proportional to

the VC pin voltage, this change causes the switch current

to be adjusted until VOUT is once again satisfied. Loop

compensation is taken care of by an RC network from the

VC pin to ground. Inside this main loop is another that sets

current limit on a cycle-by-cycle basis. This loop utilizes

current comparator A2 to control peak current. The oscil-

lator issues a set pulse to the flip-flop at the beginning of

each cycle, turning the switch on. With the switch now in

the ON state, the SW pin is effectively connected to

ground. Current ramps up in the inductor linearly at a rate

of VIN/L. Switch current is set by the VC pin voltage and

when the voltage across RSENSE trips the current com-

parator, a reset pulse will be generated and the switch will

be turned off. Since the inductor is now loaded up with

current, the SW pin will fly high until it is clamped by the

catch diode, D1. Current will flow through the diode

decreasing at a rate of (VOUT – VIN)/L until the oscillator

issues a new set pulse, causing the cycle to repeat.

The LT1310 is phase lockable up to 4.5MHz, giving the

user precise control over switching frequency. The phase

detector compares the incoming sync signal to the internal

oscillator signal. If the switching frequency is lower than

the sync signal, or if the phase lags the sync signal, then

the phase detector output will source current into the

PLL-LPF pin, driving it higher. The PLL-LPF pin is also the

input to the voltage controlled oscillator. If the sync signal

is slower than the switching frequency, the PLL-LPF pin

will sink current until the PLL-LPF pin voltage drops. When

locked, the PLL-LPF pin rests at a voltage between 0V and

1.5V. The PLL-LPF pin is capable of sinking or sourcing

approximately 140

µA.

BLOCK DIAGRA

OPERATIO

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