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AFE5808A Datasheet(PDF) 16 Page - Texas Instruments |
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AFE5808A Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 83 page  AFE5808A SLOS729D – OCTOBER 2011 – REVISED NOVEMBER 2015 www.ti.com 7.7 Switching Characteristics Typical values are at 25°C, AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, differential clock, CLOAD = 5 pF, RLOAD = 100 Ω, 14 bit, sample rate = 65MSPS (unless otherwise noted). Minimum and maximum values are across the full temperature range TMIN = 0°C to TMAX = 85°C with AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ta The delay in time between the rising edge of the input sampling 0.7 3 Aperture delay ns clock and the actual time at which the sampling occurs Aperture delay Across channels within the same device ±150 ps matching tj Aperture jitter 450 Fs rms Default, after reset, or 0 x 2 [12] = 1, LOW_LATENCY = 1 11/8 Input ADC latency clock cycles tdelay Data and frame clock Input clock rising edge (zero cross) to frame clock rising edge (zero 3 5.4 7 ns delay cross) minus 3/7 of the input clock period (T). Δtdelay Delay variation At fixed supply and 20°C T difference. Device to device –1 1 ns tRISE Data rise time Rise time measured from –100 to 100 mV, fall time measured from 0.14 ns 100 mV to –100 mV, 10 MHz < fCLKIN < 65 MHz tFALL Data fall time 0.15 tFCLKRISE Frame clock rise time Rise time measured from –100 mV to 100 mV, fall time measured 0.14 ns from 100 mV to –100 mV, 10 MHz < fCLKIN < 65 MHz tFCLKFALL Frame clock fall time 0.15 Frame clock duty cycle Zero crossing of the rising edge to zero crossing of the falling edge 48% 50% 52% tDCLKRISE Bit clock rise time Rise time measured from –100 to 100 mV, fall time measured from 0.13 ns 100 mV to –100 mV, 10 MHz < fCLKIN < 65 MHz tDCLKFALL Bit clock fall time 0.12 Zero crossing of the rising edge to zero crossing of the falling edge 46% 54% Bit clock duty cycle 10 MHz < fCLKIN < 65 MHz (1) Timing parameters are ensured by design and characterization; not production tested. 7.8 Timing Requirements Minimum values across full temperature range TMIN = 0°C to TMAX = 85°C, AVDD_5V =5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V PARAMETER DESCRIPTION MIN TYP MAX UNIT t1 SCLK period 50 ns t2 SCLK high time 20 ns t3 SCLK low time 20 ns t4 Data setup time 5 ns t5 Data hold time 5 ns t6 SEN fall to SCLK rise 8 ns t7 Time between last SCLK rising edge to SEN rising edge 8 ns t8 SDOUT delay 12 20 28 ns 16 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: AFE5808A |
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