MPC8240EC datasheet(6/52 Pages) MOTOROLA

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MPC8240 Integrated Processor Hardware Specifications

MOTOROLA

Electrical and Thermal Characteristics

1.4.1.2

Recommended Operating Conditions

Table 2 provides the recommended operating conditions for the MPC8240.

Table 2. Recommended Operating Conditions 1

Characteristic

Symbol

Recommended

Value

Unit

Notes

Supply voltage

VDD

2.5

± 5%

4, 6

Supply voltage for PCI and standard bus standards

OVDD

3.3

± 0.3

Supply voltages for memory bus drivers

GVDD

3.3

± 5%

PLL supply voltage—CPU core logic

AVDD

2.5

± 5%

4, 6

PLL supply voltage—peripheral logic

AVDD22.5 ± 5%

4, 7

DLL supply voltage

LAVDD

2.5

± 5%

4, 7

PCI reference

LVDD

5.0

± 5%

9, 10

3.3

± 0.3

9, 10

Input voltage

LVDD input-tolerant signals

Vin

0 to 3.6 or 5.75

2, 3

All other inputs

0 to 3.6

Die-junction temperature

0 to 105

°C

Notes:

1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions

is not guaranteed.

2. These signals are designed to withstand LVDD + 0.5 V DC when LVDD is connected to a 3.3- or 5.0-V DC power

supply.

3. LVDD input tolerant signals: PCI interface, PIC control, and OSC_IN signals.

4. See Section 1.9, “Ordering Information,” for details on a modified voltage (VDD) version device.

Cautions:

5. Input voltage (Vin) must not be greater than the supply voltage (VDD/AVDD/AVDD2/LAVDD) by more than 2.5 V at all

times, including during power-on reset.

6. OVDD must not exceed VDD/AVDD/AVDD2/LAVDD by more than 1.8 V at any time, including during power-on reset.

This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

7. VDD/AVDD/AVDD2/LAVDD must not exceed OVDD by more than 0.6 V at any time, including during power-on reset.

This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

8. GVDD must not exceed VDD/AVDD/AVDD2/LAVDD by more than 1.8 V at any time, including during power-on reset.

This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

9. LVDD must not exceed VDD/AVDD/AVDD2/LAVDD by more than 5.4 V at any time, including during power-on reset.

This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

10.LVDD must not exceed OVDD by more than 3.6 V at any time, including during power-on reset. This limit may be

exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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