MP7543

6

Rev. 2.00

TIMING DIAGRAM

12

11

12

Bit 1

MSB

Bit 2

Loading Register B

with Contents of Register A

LOADING REGISTER A

SR1

Strobe Input

(STB1, STB2, STB4

(Note)

LD1 AND LD2

Note:

Strobe Waveform is Inverted if

STB3 is Used to Strobe Serial Data Bits

into Register A

Bit 11

Bit 12

LSB

MP7543 Logic Inputs

MP7543 Operation

Notes

Register A Control Inputs

Register B Control Inputs

STB4

STB3

STB2

STB1

CLR

LD2

LD1

0

0

0

1

X

X

X

1

1

1

X

0

X

X

0

0

0

X

X

1

X

0

0

0

X

X

X

1

X

X

X

X

0

1

1

1

X

X

X

X

X

1

X

0

X

X

X

X

X

X

1

0

Data appearing at SRI strobed into Register A

Data appearing at SRI strobed into Register A

Data appearing at SRI strobed into Register A

Data appearing at SRI strobed into Register A

2, 3

2, 3

2, 3

2, 3

No Operation (Register A)

3

Clear Register B to code 0000 0000 0000 (Asynchronous)

1, 3

No Operation (Register B)

Load Register B with the contents of Register A

3

3

NOTES

1.

CLR = 0 Asynchronously resets Register B to 0000 0000 0000, but has no effect on Register A.

2.

Serial data is loaded into Register A MSB first, on edges shown

is positive edge,

is negative edge.

3.

0 = Logic LOW, 1 = Logic HIGH, X = Don’t Care.

Table 1. Truth Table