Philips Semiconductors

Product data

PCKV857A

100-250 MHz differential 1:10 clock driver

2003 Jul 31

3

PIN DESCRIPTION

PINS

SYMBOL

DESCRIPTION

1, 7, 8, 18, 24, 25, 31, 41, 42, 48

GND

SSTL_2 ground pins

2, 3, 5, 6, 9, 10, 19, 20, 22, 23, 26, 27, 29,

30, 32, 33, 39, 40, 43, 44, 46, 47

SSTL_2 differential outputs

4, 11, 12, 15, 21, 28, 34, 38, 46

SSTL_2 power pins

13, 14, 35, 36

SSTL_2 differential inputs

16

Analog power

17

AGND

Analog ground

37

PWRDWN

Power-down control input

FUNCTION TABLE

INPUTS

OUTPUTS

PWRDWN

CLK

CLK

PLL ON/OFF

L

L

H

Z

Z

OFF

L

H

L

Z

Z

OFF

H

L

H

L

H

L

H

ON

H

H

L

H

L

H

L

ON

< 20 MHz

< 20 MHz

Z

Z

OFF

NOTES:

H = HIGH voltage level

L = LOW voltage level

Z = HIGH impedance OFF-state

X = don’t care

2. Additional feature that senses when the clock input is less than 20 MHz and places the part in sleep mode.

BLOCK DIAGRAM

PLL

37 - PWRDWN

13 - CLK

14 - CLK

SW00692