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LVCMOS OUTPUT PARAMETER, Y3

JITTER CHARACTERISTICS

CDCM1804

SCAS697E – JULY 2003 – REVISED MAY 2005

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0

200

MHz

Output skew between the LVCMOS out-

1.3

1.6

2.1

ns

put Y3 and LVPECL outputs Y[2:0]

Part-to-part skew

Y3, see Note B in Figure 8.

300

ps

High-level output voltage

2.4

V

2

0.1

Low-level output voltage

0.5

V

0.8

High-level output current

–29

mA

Low-level output current

37

mA

High-impedance-state output current

±5

µA

Output capacitance

2

pF

–150

150

ps

Propagation delay rising edge from IN to

1.6

2.6

ns

Y3

Propagation delay falling edge from IN

1.6

2.6

ns

to Y3

Output rise slew rate

20% to 80% of swing, see Figure 10.

1.4

2.3

V/ns

Output fall slew rate

80% to 20% of swing, see Figure 10.

1.4

2.3

V/ns

(1)

Operating the CDCM1804 LVCMOS output above the maximum frequency does not cause a malfunction to the device, but the Y3

output will not achieve enough signal swing to meet the output specification. Therefore, the CDCM1804 can be operated at higher

frequencies, while the LVCMOS output Y3 becomes unusable.

(2)

For a 200-MHz signal, the 150-ps error would result in a duty cycle distortion of

±3% when driven by an ideal clock input signal.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

12 kHz to 20 MHz,

0.15

divide-by-1 mode

Additive phase jitter from input to

ps rms

LVPECL output Y[2:0], see Figure 2. 50 kHz to 40 MHz,

0.25

divide-by-1 mode

0.25

divide-by-1 mode

Additive phase jitter from input to

ps rms

LVCMOS output Y3, see Figure 3.

0.4

divide-by-1 mode

7