RT9641AC32 datasheet(7/14 Pages) RICHTEK

7 / 14 page

RT9641A/B

DS9641A/B-03 March 2002

www.richtek-ic.com.tw

12V (Pin 14)

Connect this pin to the ATX (or equivalent) 12V

output. This pin is used to monitor the status of the

power supply as well as provide bias for the NMOS-

compatible output drivers. 12V presence at the chip

in the absence of bias voltage, or severe 12V

brownout during active states (S0, S1) operation can

lead to chip misbehavior. RT9641A/B refuses

entering active state before 12V power ready.

DRV2 (Pin 15)

For the 2.5V RDRAM systems, connect this pin to the

base of a suitable NPN transistor. This pass

transistor regulates the 2.5V(2.6V) output from the

ATX 3.3V during active states operation. For 3.3V

SDRAM systems connect this pin to the gate of a

suitable N-MOS transistor or the base of a suitable

NPN transistor.

VSEN2 (Pin 16)

Connect this pin to the memory output (VOUT2). In

sleep states, this pin is regulated to 2.5V(2.6V) or

3.3V(3.43V) (based on RSEL) through an internal

pass

transistor

capable

delivering

300mA

(Typically). The active-state voltage at this pin is

regulated through an external NPN or NMOS

transistor connected at the DRV2 pin for both

2.5V(2.6V) and 3.3V(3.43V) setting. During all

operating states, the voltage at this pin is monitored

for under-voltage events.

Description

Operation

The RT9641A/B controls 3 output voltages. It is

designed for microprocessor computer applications

with 3.3V, 5V, 5VSB, and 12V outputs from an ATX

power supply. The IC is composed of two linear

controllers supplying the PCI slots' 3.3VAUX power

(3.3VDUAL, VOUT1) and the 2.5V RDRAM or 3.3V

SDRAM memory power (2.5V/3.3V(2.6V/3.43V) VMEM,

VOUT2), and a dual switch controller supplying the

5VDUAL voltage (VOUT3). In addition, all the control and

monitoring functions necessary for complete ACPI

implementation are integrated into the RT9641A/B.

Initialization

The RT9641A/B automatically initializes upon receipt

of input power. The Power-On Reset (POR) function

continually monitors the 5VSB input supply voltage,

initiating soft-start operation after it exceeds its POR

threshold (in S4/S5 states). The 5VSB POR trip event

is also used to lock in the memory voltage setting

based on RSEL.

The RT9641A/B forces the operation mode to start

from S4/S5 states at POR releasing.

Operational Truth Tables

The EN3VDL and EN5VDL pins offer a host of choices

in terms of the overall system architecture and

supported features. Tables 1~3 describe the truth

combinations pertaining to each of the three outputs.

Table 1. 3.3VDUAL Output (VOUT1) Truth Table

EN3VDL S5 S3 3V3D

Comments

3.3V

S0, S1 States (Active)

3.3V

Note

Maintains Previous State

3.3V

S4/S5

3.3V

S0, S1 States (Active)

3.3V

Note

Maintains Previous State

S4/S5

Note: Combination not allowed.

As seen in Table 1, EN3VDL simply controls whether

the 3.3VDUAL plane remains powered up during S4/S5

sleep state.

RT9641AC32 Datasheet(PDF) 7 Page - Richtek Technology Corporation

RT9641AC32 Datasheet(HTML) 7 Page - Richtek Technology Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Datasheet Download

Link URL