SDA

SCL

VDD

RPU

RPU

RPU

RPU

RPU

RPU

RPU

RPU

C

Master

C

Slave

GND

GND

GND

SDA

SCL

GND

SDA

SCL

SDA

SCL

SDA

SCL

DAC

Slave

ADC

Slave

21

ISO1540, ISO1541

www.ti.com

SLLSEB6D – JULY 2012 – REVISED DECEMBER 2016

Product Folder Links: ISO1540 ISO1541

Submit Documentation Feedback

Copyright © 2012–2016, Texas Instruments Incorporated

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

communication in half-duplex mode.

VDD by resistors (see Figure 27). Pulling the line to ground is considered a logic zero while letting the line float is

a logic one. This logic is used as a channel access method. Transitions of logic states must occur while the SCL

pin is low. Transitions while the SCL pin is high indicate START and STOP conditions. Typical supply voltages

are 3.3 V and 5 V, although systems with higher or lower voltages are allowed.

nodes can communicate on the same bus. In praxis, however, the number of nodes is limited by the specified,

total bus capacitance of 400 pF, which restricts communication distances to a few meters.

The specified signaling rates for the ISO1540 and ISO1541 devices are 100 kbps (standard mode), 400 kbps

(fast mode), 1 Mbps (fast mode plus).

The bus has two roles for nodes: master and slave. A master node issues the clock and slave addresses, and

also initiates and ends data transactions. A slave node receives the clock and addresses and responds to

requests from the master. Figure 28 shows a typical data transfer between master and slave.