PC97317 datasheet(52/272 Pages) NSC

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Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)

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3.5.1

The KBC DBBOUT Register, Offset 60h,

Read Only

The DBBOUT register transfers data from the keyboard

controller to the PC87317VUL. It is written to by the key-

board controller and read by the PC87317VUL for transfer

to the PC. The PC may be notified of the need to read data

from the KBC by an interrupt request or by polling the Out-

put Buffer Full (OBF) bit (bit 0 of the KBC STATUS register

described in Section 3.5.3 "The KBC STATUS Register").

3.5.2

The KBC DBBIN Register, Offset 60h (F1 Clear)

or 64h (F1 Set), Write Only

The DBBIN register transfers data from the PC87317VUL

system to the keyboard controller. (This transaction is trans-

parent to the user, who should program the device as if di-

rect access to the registers were in effect.)

When data is received in this manner, an Input Buffer Full

(IBF) internal interrupt may be generated in the KBC, to deal

with this data. Alternatively, reception of data in this manner

can be detected by the KBC polling the Input Buffer Full bit

(IBF, bit 1 of the KBC STATUS register).

3.5.3

The KBC STATUS Register

The STATUS register holds information regarding the sys-

tem interface status.The bitmap below shows the bit defini-

tion of this register. This register is controlled by the KBC

firmware and hardware, and is read-only for the system.

FIGURE 3-8. KBC STATUS Configuration Register Bit-

map

Bit 0 - OBF, Output Buffer Full

A 1 indicates that data has been written into the DB-

BOUT register by the KBC. It is cleared by a system

read operation from DBBOUT.

Bit 1 - IBF, Input Buffer Full

When a write operation is performed by the host system,

this bit is set to 1, which may be set up to trigger the IBF

interrupt. Upon executing an IN A, DBB instruction, it is

cleared.

Bit 2 - F0, General Purpose Flag

A general purpose flag that can be cleared or toggled by

the keyboard controller firmware.

Bit 3 - F1, Command/Data Flag

This flag holds the state of address line A2 while a write

operation is performed by the host system. It distin-

guishes between commands and data from the host

system. In this device, a write with A2 = 1 (hence F1 =

1) is defined as a command, and A2 = 0 (hence F1 = 0)

is data.

Bits 7-4, General Purpose Flags

These flags may be modified by KBC firmware.

3.6

INSTRUCTION TIMING

The KBC clock is first divided by 3 to generate the state tim-

ing, then by 5 to generate the instruction timing. Thus each

instruction cycle consists of five states and 15 clock cycles.

Most keyboard controller instructions require only one in-

struction cycle, while some require two cycles. Refer to the

8042 or PC87323VUL instruction set for details.

FIGURE 3-9. Instruction Timing

76543210

Reset

OBF Output Buffer Full

IBF Input Buffer Full

F0 General Purpose Flag

F1 Command or Data Flag

General Purpose

Flags

KBC Status Register

Offset 64h

Read Only

1 Instruction Cycle = 15 Clock Cycles

KBC CLK

PC97317 Datasheet(PDF) 52 Page - National Semiconductor (TI)

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