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FIGURE 73. EPP 1.7 Address Read

EPP 1.7 Data Write and Read

This procedure writes to the selected peripheral de-

vice or register.

An EPP 1.7 data read or write operations are similar

to the EPP 1.7 address read or write operations, ex-

cept that the data strobe (DSTRB signal), and a data

and the address register respectively.

EPP Revision 1.7 Zero Wait State (ZWS)

Address and Data Write and Read

Operations

To configure the device for zero wait states, set bit 5

of FCR to 1 and clear bit 6 of FCR to 0. When bit 5 of

FCR is 1, the EPP revision is always 1.7, i.e., it is not

affected by bit 1 of PCR.

The following procedure performs a short write to the

selected peripheral device or register. See also Fig-

ure 74.

1. The system writes a byte to the EPP address reg-

ister. WR goes low to latch D7-0 into the data reg-

ister. The latch drives the data register to PD7-0.

2. The EPP first pulls WRITE low, and then pulls

ASTRB low to indicate that data has been sent.

3. If WAIT was high during the system write cycle,

ZWS goes low and IOCHRDY stays high.

4. When the system pulls WR high, the EPP pulls

ASTRB, ZWS and then WRITE to high. The EPP

can change PD7-0 only when WRITE and ASTRB

are high.

5. If the peripheral is fast enough to pull WAIT low

before the system terminates the write cycle, the

EPP pulls IOCHRDY to low, but does not pull ZWS

to low, thus carrying out a normal (non-ZWS EPP

1.7) write operation.

FIGURE 74. EPP Write with Zero Wait States

A read operation is similar, except for the data direc-

tion, activation of RD instead of WR, and WRITE

stays high.

EPP 1.7 zero wait state data write and read opera-

tions are similar to EPP zero wait state address write

and read operations, with the exception that the data

strobe (DSTRB signal), and a data register, replace

the address strobe (ASTRB signal) and the address

EPP 1.9 Address Write

The following procedure selects a peripheral or regis-

ter as shown in Figure 75.

1. The system writes a byte to the EPP address reg-

ister.

2. The EPP pulls IOCHRDY low, and waits for WAIT

to become low.

3. When WAIT becomes low, the EPP pulls WRITE

to low and drives the latched byte onto PD7-0. If

WAIT was already low, steps 2 and 3 occur con-

currently.

4. The EPP pulls ASTRB low and waits for WAIT to

become high.

5. When WAIT becomes high, the EPP stops pulling

IOCHRDY low, and waits for WR to become high.

6. When WR becomes high, the EPP pulls ASTRB

high, and waits for WAIT to become low.

7. If no EPP write is pending when WAIT becomes

low, the EPP pulls WRITE to high. Otherwise,

WRITE remains low, and the EPP may change

PD7-0.

D7-0

WAIT

ASTRB

WRITE

PD7-0

IOCHRDY

ZWS

D7-0

WAIT

DSTRB or

WRITE

PD7-0

IOCHRDY

ZWS

ASTRB

PC97338 Datasheet(PDF) 132 Page - National Semiconductor (TI)

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